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PDF CDP1835C Data sheet ( Hoja de datos )
| Número de pieza | CDP1835C | |
| Descripción | CMOS 2048-Word x 8-Bit Static Read-Only Memory | |
| Fabricantes | GE | |
| Logotipo |  |
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Read-Only Memories (ROMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1835C
MA7
MA6
MAS
MA4
MA3
MA2
MAl
MAO
BUSO
BUSI
BUS2
VSS
I 24 Voo
2 23 TPA
3 22 cn
4 21 CSI
5 20 CS2
6 19 MRli
7 18 CEO
8 17 BUS7
• 9 16 BUS6
10 IS BUSS
II 14 BUS4
12 13 BUS3
TOP VIEW
92CS-33188
TERMINAL ASSIGNMENT
CMOS 2048-Word X 8-Bit Static
Read-Only Memory
Features:
• Interfaces with CDP1800-series microprocessors
(fCIOCk::; 5 MHz) without additional components
• On-chip address latch
• On-chip address decoder pro~ides programmable location within 64K
memory space
• Three-state outputs
The RCA-COP1835C is a 16384-bit mask-programmable
CMOS read-only memory, organized as 2048 words x 8 bits
and is completely static: no clocks required. It will directly
interface with COP1800-series microprocessors that have
clock frequencies up to 5 MHz without additional
components.
The COP1835C responds to a 16-bit address multiplexed on
8 address lines. Address latches are provided on-chip to
store the 8 most significant bits of the 16-bit address. By
mask option, this ROM can be programmed to operate in
any 2048-word block of 64K memory space. The polarity of
the high address strobe (TPA), MAD, CEI, CS1, and CS2 are
user mask-programmable.
The Chip-Enable output signal (CEO) is "high" when the
device is selected. Terminals CEO and CEI can be connected
in a daisy chain to control selection of RAM memory in a
microprocessor system without additional components.
The COP1835C has a recommended operating voltage
range of 4 to 6.5 volts.
The COP1835C is supplied in 24-lead heremetic dual-in-
line side-brazed ceramic packages (0 suffix) and 24-lead
dual-in-line plastic packages (E suffix).
RAM
CPU
CDPIBOO
SERIES
I/O
Fig. 1 - Typical CDP1800 Series microprocessor system.
92CM-33192RI
File Number 1267
742 ________________________________________________________________
1 page  
Read-Only ....emorles (ROMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1835C
NA
HIGH ORDER
ADDRESS BYTE
LOW ORDER
ADDRESS BYTE
TPA
II1
NRO
i--'AS-
I - - 1 - - ' AH
-' PAW .....
'I
'RSU I.-
II\.
'AVQV
141
'SVQV
- -, RXCL
-J~
, RXQZ 1--
CS I21
HIGH IMPEDANCE
BUS
131
CEO
--r--' CEJ:O
---..,
eEl:
'SVQX-
'0
OUTPUT
JACTIVE
LOW
- t SXQZ 1-'-
VALID DATA
r---'CA-
'---
9ZCM - 37229
FIg 4 - Tlmmg dIagram.
Notes:
(1) MRD must be valid on or before the trailing edge of
TPA. (Output will be trl-stated and the ROM powered
down when MRD Is not valid.
(2) CS (CS1 and CS2) controls the output bullers only.
Output will be trl-stated when either CS1 or CS21s not
valid.
(3) CEO Is high when ROM Is enabled.
(4) Provided tAVQV Is satlslled.
746 _______________________________________________________________
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet CDP1835C.PDF ] | |
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