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CDP68HC68R2 Schematic ( PDF Datasheet ) - GE

Teilenummer CDP68HC68R2
Beschreibung CMOS 128-Word and 256-Word by 8-Bit Static RAMs
Hersteller GE
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Gesamt 7 Seiten
CDP68HC68R2 Datasheet, Funktion
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
Product Preview
M~~~O:I :O:SI
NC 3
VSS 4
VIEWTOP
6 CE
5 ss
92CS-3786!5
TERMINAL ASSIGNMENT
CDP68HC68R1, CDP68HC68R2
CMOS 128-Word (CDP68HC68R1) and
256-Word (CDP68HC68R2) by
8-Bit Static RAMs
Features:
• Fully static operation
• Operating voltage range:
3 VtoS.S V
• Typical standby current=1 pA
• Directly compatible with
RCA/Motorola SPI bus
• Separate data input and three-
state data output pins
• Input data and clock buffers
gated off with chip enable
• Automatic sequencing for fast
multiple-byte accesses
• Low minimum data retention
voltage: 2 V
• Wide operating temperature
range: -40· C to +8S· C
The RCA CDP68HC68R1 and CDP68HC68R2are 128-word
and 256-word by 8-bit static random-access memories,
respectively. The memories are intended for use in systems
utilizing a synchronous serial three-wire (clock, data in, and
data out) interface where minimum package size,
interconnect wiring, low power, and simplicity of use are
desirable. These parts will interface directly with RCA's
CDP68HC05D2, CDP68HC05C4, and CDP68HC05C8
microcomputers (providing the CPHA bit in the
microcomputer's SPI Control Register is set equal to 1). The
CDP68HC68R1 and CDP68HC68R2 are also compatible
with general-purpose microcomputers, including RCA's
CDP1804A and CDP6805 family, by utilizing I/O bits forthe
SPI (Serial Peripheral Interface) bus. Other industry
microcomputers such as the 80C51 can also interface to
these serial RAM's.
The CDP68HC68R1 and CDP68HC68R2 are supplied in
8-lead plastic Mini-DIP packages (E suffix).
TRUTH TABLE
MODE
DISABLED
& RESET
READ
OR
WRITE
SHIFT
CE
L
X
H
H
SIGNAL
B
SCK
MOSI
MISO
X
INPUT
INPUT
H
DISABLED
DISABLED
HIGHZ
CPOL=O,
' -L
-.rCPOL=1,
DATA BIT
LATCH
HIGHZ
DURING WRITE,
CURRENT DATA BIT
DURING READ
fCPOL=O,
L
' - -CPOL=1,
X NEXT DATA
BIT
NOTE:
MISO remains at a High Z until8 bits of data are ready to be shifted out during a Read and it remains at a HIGH Z during the
entire Write cycle.
The CPHA bit must be set = 1 in the Serial Perpherial Control Register of 6805 microcomputers in order to Communicate
with these devices.
File Number 1544
_______________________________________________________________ 679






CDP68HC68R2 Datasheet, Funktion
Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP68HC68R1, CDP68HC68R2
MOSI +'rWrT+!II
/
CE'SS
SCK
SCK
Fig. 6 - Page/Device byte timing waveforms.
OON »»)) )))
Fig. 7 - WRITE cycle timing waveforms.
MOS I -h'"t-I+N
Mrso --------~--------~~--~~--------~_at
CE -S5
SCK
Fig. 8 - READ cycle timing waveforms.
684 ______________________________________________________________

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CDP68HC68R2CMOS 128-Word and 256-Word by 8-Bit Static RAMsGE
GE

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