Datenblatt-pdf.com


CDM6264 Schematic ( PDF Datasheet ) - GE

Teilenummer CDM6264
Beschreibung CMOS 8192-Word by 8-Bit LSI Static RAM
Hersteller GE
Logo GE Logo 




Gesamt 6 Seiten
CDM6264 Datasheet, Funktion
Random-Access Memories (RAMs) _______________________
CDM6264
NC
AI2
A7
A.
AS
••
A'
A2
AI
AD
1/01
1/02
I103
v••
6
10
.."12
I.
28 VDD
27 iVf
2. CE2
. .,2. A8
2.
.11
.'022 OE
21
m20
19 I/08
I. 1/07
17 I./08
I. 1/05
I. 1/04
TOP VIEW 91tS- 31209
TERMINAL ASSIGNMENT
CMOS 8192-Word by 8-Bit
LSI Static RAM
Features:
• Fully static operation
• Single power supply: 4.5 V to 5.5 V
• All inputs and outputs directly TTL
compatible
• Industry standard 2B-pin configuration
• Input address buffers gated off
with chip disable
• 3-state outputs
The RCA-CDM6264 is a 8192-word by B-bit static random-
access memory. It is designed for use in memory systems
where high-speed. low power and simplicity in use are
desirable. This device has common data input and data
output and utilizes a single power supply of 4.5 V to 5.5 V.
Either chip enable (00 or CE2). when not valid. will gate off
the address and output buffers and power down the chip to
minimum standby power with inputs toggling. The output
enable (OE) controls the. output buffers to eliminate bus
contention.
The CDM6264 is supplied in a 28-lead dual-in-line plastic (E
suffix) package.
AI2
All
A,AID
A. INPUT
ADDRESS
XV
DECODE
aUFFERS
A7
A'
..A.
A'
A'
AI
AO ENABLE
256. US
MEMORY
MATRIX
INPUTI
OUTPUT
DATA
BUFFERS
1/0'8
1/07
1/06
1/05
I104
1/03
1./02
:t/01
CiT
......-.-0 "'DO
CE' c~~~~gL 1-_ _ _ _ _ _ _ _ _ _ _ _--' 4-----0 Vss
Wi
9ZCIII-57210
0[
Fig. 1 - Functional block diagram.
CDM6284-3 FDM6264-21
Access Time (max)
150 ns
200 ns
Output Enable Time
(max.)
70 ns
70 n.
Operating Current
(max.)
45mA
45mA
Standby Current
100., (max.)
100pA 200pA
Operating Temp.
O·C to -40·C to
Range:
+70·C
+85·C
Data Retention Voltage:
O°CST",S+70°C
O°C::S; TA S +85°C
-40°CST",<0°C
2V min
-
-
-
2Vmin
4Vmin.
TRUTH TABLE
CE1 CE2 OE WE
H
X
L
L
-L
L - LOW
XX X
LXX
HLH
HXL
HH H
H - HIGH X - H OR L
AOTOA12
X
X
STABLE
STABLE
STABLE
MODE
NOT SELECTED
NOT SELECTED
READ
WRITE
OUTPUT DISABLE
DATA 110
HIGHZ
HIGHZ
DATA OUT
DATA IN
HIGHZ
DEVICE
CURRENT
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
File Number 1505
M2 ____________________________________________________________






CDM6264 Datasheet, Funktion
;...-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
CDM6264
DATA RETENTION CHARACTERISTICS, See Fig. 4.
CHARACTERISTIC
Minimum Data Retention
Voltage
VOR
Data Retention Quiescent
Current
looDR
Chip Disable to Data
Retention Time
Recovery to Normal
Operation Time
"l"e = Read Cycle Time
teoR
tR
TEST CONDITIONS
CEl ::::: Voo-0.2 V,or CE2 :0; 0.2 V:
O°C:O; T.:O; +70°C
O°C:O; T.:O; +85°C
-40° C < TA < 0° C
GEl ,CE2 ::::: Voo-0.2 V.
or CE2 :0; 0.2 V:
Voo =3 V, O°C:O; TA:O; +70°C
Voo - 3 V, O°C:O; TA:O; +85°C
Voo =4 V, -40°C:O; TA < O°C
See Fig. 4
See Fig. 4
LIMITS
CDM6264-3 CDM6264-21
Min. Max. Min. Max.
2- - -
--
2-
- - 4-
- 50 - -
- - - 100
- - - 100
0-
0-
"'tRC -
"'tRC -
UNITS
V
pA
ns
DATA RETENTION WAVEFORM 1 (CEl CONTROL)
VDD
C El / ' 22V~
DATA RETENTION WAVEFORM 2 (CE2 CONTROL)
DATA
RETENTlON-----i
MODE
VDD
"",!'''' '. 1/TTTT
CE2
~~~~~~~~0--4-V---- --0-.-4-~V~~~~-L-L-_- ___C__E_2_$_0_._2 _V________-----_-_
92CM -37208
Fig 4 - Low Vee data-retention timing waveforms.
_____________________________________________________________________ 647

6 Page







SeitenGesamt 6 Seiten
PDF Download[ CDM6264 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
CDM6264CMOS 8192-Word by 8-Bit LSI Static RAMGE
GE
CDM6264CMOS LSI Static RAMHarris Semiconductor
Harris Semiconductor
CDM6264ACHigh Reliability CMOS LSI Static RAMRCA Solid State
RCA Solid State

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche