PDF CDP6823 Data sheet ( Hoja de datos )

Número de pieza	CDP6823
Descripción	CMOS Parallel Interface
Fabricantes	GE
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CMOS Peripherals CDP6823 TERMINAL ASSIGNMENT PCI Voo PCI PC3 PCO PAD PC4/CA1 PC~/CA2 PAl PC6/CB Poll PCrlce2 PAS P80 Pol'" P8' PAil P82 PAl PIJ PAl' P8" ADO P85 AO' PBe mA02 AD3 PS1 AD4 mrT' An os ADe R/ii' V"A01 ---.=-_-',"',- AS Jr TOP VIEW 4G-Lead Plcklll" Advance Information CMOS Parallel Interface Featurel: • Four port C I/O pins may be used as Control Lines for: • 24 Individual programmed I/O pins Four interruput inputs • MOTEL circuit for bus compatibility Input byte latch with many microprocessors Output pulse • Multiplexed bus compatible with: Handshake activity CDP6805E2 and competitive • 15 registers addressed as memory microprocessors locations • Data direction registers for ports A, S, • Handshake control logic for Input and andC output peripheral operation • Reset Input to clear interrupts and • Interrupt output pin Initialize Internal registers • 3 volt to 5.5 volt operating Voo The RCA-C0P6823 CMOS parallel interface (CPI) provides a universal means of interfacing external signals with the C0P6805E2 CMOS microprocessor and other multiplexed bus microprocessors. The unique MOTEL circuit on-chip allows direct Interfacing to most industry CMOS microprocessors, as well as many NMOS MPUs. The C0P6B23 CPI includes three bidirectlonal8-bit ports or 24 1/0 pins. Each 1/0 line may be separately established as an Input or an output under program control via data direction registers associated with each port. Using the bit change and test Instructions of the C0P6805E2, each individual I/O pin can be separately accessed. All port registers are readlwrlte bytes to accommodate read- modify-write Instructions. The C0P6B23Is supplied In a 40-lead hermetic dual-in-line side-brazed ceramic package (0 suffix), In a 4o-Iead dual- In-line plastiC package (E suffix) and In a 44-lead plastiC chlp-carrler package (Q suffix). The RCA-COP6823 is equivalent to and is a direct replacement for the Industry type MC146823. '" 'A""" AD5 ASEDS RI\IV Control R"E"S'rT Inputs " TERMINAL ASSIGNMENT PA' Ne PA! PC7lCB2 PA' PA. 'D PBD PB. PAl 11 12----=f--- - ..PA7 IADD n TOplYIEW ~!5 PB. PB' 33 PB. AD' ~ ADZ 15 I ~ PB' 31 PBe AD! 16 30 pa? Ne 17 29 fRO 18 19 20 21 22 23 24 25 26 27 28 = It;> I~ : I~ ~ Ii! :!IE .. 92CS -40940 44-L.ad Pla.tlc Chip-Carrier Packlll' Fig. 1 - Functional block diagram. '"Pc> PC3 PC4ICAI PC5/CA2 pee/CBI PC71CB2 File Number 1377 598 ______________________________________________________________ 1 page CMOS Peripherals CDP6823 CONTROL TIMING (VDD=5 Vdc ± 10% vss-o Vdc TA -O°C to 70°C) Parameter Interrupt Response (tnput Modes 1 and 3) Delay, CAl (CB1) Active Transition to CA2 (CB2) High (Output Mode 0) aDelay, CA2 Transition from Positive Edge of AS (Output Modes and 1) aDelay, CB2 Transition from Negative Edge of AS (Output Modes and 1) CA2/CB2 Pulse Width (Output Mode 1) Delay, VDD Rise to R'ES'IT High Pulse Width, RESET TBD= To be determined Symbol tlRQR tC2 tA2 tB2 tpw tRLH tRW Min TBD TBD TBD TBD TBD TBD TBD Max - - - TBD - Unit I's I's I's I's ns I's ns iAORESPONSE (INPUT MODES 1 AND 3) CAl CA2 =£'---t-""9-- CA2/CB2 DELAY (OUTPUT MODE 1) r Read Pl DA/Wrlte Pl DB Cycle AS CA2/CB2 DELAY (OUTPUT MODE 0) ,~CA1/CBl _ _ _ _ _ _ _ _ _ __ -----'+f' tC2 CA2/CB2 CA2/CB2 AS Cycle Fig. 6 - Control timing diagrams. 602 ______________________________________________________________ 5 Page CMOS Peripherals CDP6823 D.scrlptlon: Data written into PDA is latched into the port A output latch (see Fig, 3) regardless olthe state of DDRA. Output pins, as defined by DDRA, assume the logic levels of the cor- responding bits in the PDA output latch, The PDA output latch allows the user to read the state of the port A output data. If the input latch is not enabled, a read of any port A data register reflects the current state of the port A input pins as defined by DDRA and the contents of the output latch for output pins. Writes into Pl DA or P2DA have no effect upon the output pins or the output data latch. Users are recommended to initialize the port A output latch before changing any pin to an output via the DDRA. MPU accesses of Pl DA or P2DA are primarily used to affect handshake and status activity. A summary of the effects on the status and warning bits of port A data register accesses is given in Table 4. For more information, see HANDSHAKE OPERATION and Control R.glst.r A (CRA) under REG- ISTER DESCRIPTION. Reset has no effect upon the contents of any port A data register. R.glat.r Nam••: Port B Data Registers (PDB, P1DB, P2DB) R.gl.t.r Addr.....: . $3 (PDB), $C (Pl DB), $D (P2DB) R.glst.r Bit.: 7 I I I I I I IBit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 Bit 2 Bit 1 o Bit 0 Purpos.: These three registers serve different purposes. The Port B data registers are used to read input data and to latch data written to the port B output pins, Writes to PDB and Pl DB affect the contents of the output data latch while writes to P2DB do not affect the output data latch. Pl DB and P2DB accesses additionally affect handshake and status activity for PC6/CBl and PC7/CB2, Description: Data written into PDB and Pl DB port B registers is latched into the port B output latch (see Fig. 3) regardless of the state of DDRB. Output pins, as defined by DDRB, assume the logic levels of the corresponding bits in the port B output latch. Reads of any port B data registers reflect the contents of the output data latch for output pins and the current state of the input pins (as determined by DDRB), Users are recommended to initialize the port B output latch before changing any pin to an output via the DDRB, MPU accesses of Pl DB or P2DB are primarily used to affect handshake and status activity. A summary of the effects on status and warning register bits of port B data register accesses is given in Table 5. For more information, see HANDSHAKE OPERATION or Control Register B (CRB) under REGISTER DESCRIPTION. Reset has no effect upon the contents of any port B data register. TABLE 4 - SUMMARY OF EFFECTS ON HANDSHAKE STATUS. WARNING BITS. AND OUTPUT LATCH BY PORT A DATA REGISTER ACCESSES Register Accessed PDA PlDA P2DA HSR Bit None HSA 1 cleared to a logiC zero HSA2 cleared to a logiC zero HWR Bit None HWAl loaded Into buffer latch HWA2 loaded Into buffer latch Handshake Reaction None CA2 goes low If output modes o or 1 are selected In the CRA CA2 goes low If output modes o or 1 are selected In the CRA Output Latch Read Write Yes Yes Yes No Yes No TABLE 5 - SUMMARY OF EFFECTS ON HANDSHAKE STATUS. WARNING BITS. AND OUTPUT LATCH BY PORT B DATA REGISTER ACCESSES Register Accessed PDB PlDB P2DB HSR Bit None HSBl cleared to a logiC zero HSB2 cleared to a logiC zero HWR Bit None HWBl loaded Into buffer latch HWA2 loaded Into buffer latch Handshake Reaction None CB2 goes low If output modes o or 1 are selected In the CRB CB2 goes low If output modes a or 1 are selected In CRB Output Latch Read Write Yes Yes Yes Yes Yes No 608 _________________________________________________________________ 11 Page

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