Datenblatt-pdf.com


CDP6818A Schematic ( PDF Datasheet ) - GE

Teilenummer CDP6818A
Beschreibung CMOS Real-Time Clock
Hersteller GE
Logo GE Logo 




Gesamt 19 Seiten
CDP6818A Datasheet, Funktion
__________________________ CMOS Peripherals
Advance Information
TERMINAL ASSIGNMENT
MOT
OSCI
24 Voo
23 sew
OSC2
ADO
22 PS
21 CKour"
ADI
AD2
AD3
AD4
AD5
7
8
9
20 C KFS
19 TAo
18 'R"E"SE'T
17 os
16 STBY
AD6
10
'5 R/W
"AD7
VSS
'2
cs'4 AS
'3
92C5-42690
24-Lead Dual-In-Llne Package
CDP6818A
CMOS Real-Time Clock Plus RAM
Features:
• Low-power, high-speed CMOS
• Internal time base and oscillator
• Counts seconds, minutes, and hours of the day
• Counts days of the week, date, month, and year
• 3 V to 6 V operation
• Time base input options: 4.194304 MHz, 1.048576 MHz, or 32.768 kHz
• Time base oscillator for parallel resonant crystals
• 40 to 200 pW typical operating power at low frequency time base
• 4.0 to 20 mW typical operating power at high frequency time base
The COP6818A Real-Time Clock plus RAM is a peripheral
device which includes the unique MOTEL concept for use
with various microprocessors, microcomputers, and larger
computers. This part combines three unique features: a
complete time-of-day clock with alarm and one hundred
year calendar, a programmable periodic interrupt and
square-wave generator, and 50 bytes of low-power static
RAM. The COP6818A uses high-speed CMOS technology
to interface with 1 MHz processor buses, while consuming
very little power.
The Real-Time Clock plus RAM has two distinct uses. First,
it is designed as a battery powered CMOS part (in an
otherwise NMOS/TTL system) including all the common
battery backed-up functions such as RAM, time, and
calendar. Secondly, the COP6818A may be used with a
CMOS microprocessor to relieve the software of the
timekeeping workload and to extend the available RAM of
an MPU such as the C0P6805E2.
T£RMINAL ASSIGNMENT
c ;t
>C
o
u>
u>
..
4 3 2 1 28 27 26
PIN'~ADO
AD.
AD2
25 CKOUT
24 CKFS
23 IRQ
AD3
22 RESET
AD4
TOPVIEW
21 OS
AD5
'0
20 ST BY
"N/C
'9
,2 13 14 '5 16 17 18
R/ii
.C
"
z~
...
C
"
!ll~
u>
"
~
Z
92CS-42691
28-Lead Plastic Chip-Carrier Package
(Q Suffix)
• Binary or BCD representation of time, calendar, and
alarm
• 12- or 24-hour clock with AM and PM in 12-hour mode
• Daylight savings time option
• Automatic end of month recognition
• Automatic leap year compensation
• Microprocessor bus compatible
• Selectable between Motorola and competitor bus timing
• Multiplexed bus for pin efficiency
• Interfaced with software as 64 RAM locations
• 14 bytes of clock and control registers
• 50 bytes of general purpose RAM
• Status bit indicates data integrity
• Bus compatible interrupt Signals (IRQ)
• Three interrupts are separately software maskable and
testable
Time-of-day alarm, Once-per-second to
Once-per-day
Periodic rates from 30.5 ps to 500 ms
End-of-clock update cycle
• Programmable square-wave output signal
• Clock output may be used as microprocessor clock input
at time base frequency +1 or +4
lEI
The COP6818A is supplied in a 24-lead dual-in-line plastic
package (E suffix). in a 24-lead dual-in-line side-brazed
ceramic package (0 suffix) and in a 28-lead plastic chip
carrier package (Q suffix).
File Number 2041
------_________________________________________________________ 579






CDP6818A Datasheet, Funktion
CMOS Perlpherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP6818A
TABLE 1 - SWITCHING CHARACTERISTICS (Vss = 0 Vdc, T. = TL to TH)
CHARACTERISTIC
Oscillator Startup
Reset Pulse Width
Reset Delay Time
Power Sense Pulse Width
Power Sense Delay Time
lAO Release from OS
IRQ Release from RESET
VRT Bit Delay
Voo = 3.0 Vdc
MIN.
MAX.
Voo = 5.0 Vdc ± 10%
MIN.
MAX.
UNITS
tAC -
300 -
100 ms
tAWL 25
-
5 - p.s
tALH 25
-
5 - p.s
t.WL 25
-
5 - p.s
tPLH 25
-
5-
p.s
t'AOS -
10 -
2 p.s
tlAR -
10 -
2 p.s
tVRTD
-
10 -
2 p.s
os
RESET
\ VLOW
IRO ) VHIGH
tlROS
NOTE VHIGH=VOO-20V, VLOW=08V, forVOO=50V ±1O%
.04.
"
Fig, 5 - IRQ release delay,
~
.J
'IRR
92CS-42696
Test
POint
130 pF
VOD
2k
liRO Only)
402 k
0-----.Test POint
All Outputs Except OSC2 I See Figure 101
Fig, 6 - TTL equivalent test load,
92CS-42697
584 _________________________________________________________________

6 Page









CDP6818A pdf, datenblatt
CMOS Perlpherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP6818A
TABLE 3 - TIME, CALENDAR, AND ALARM DATA MODES
ADDRESS
LOCATION
FUNCTION
DECIMAL
RANGE
RANGE
EXAMPLE *
BINARY
DATA MODE
BCD
BINARY
BCD
DATA MODE DATE MODE DATA MODE
0
Seconds
0-59
$00-$38
$00-$59
15
1
Seconds Alarm
0-59
$00-$38
$00-$59
15
2
Minutes
0-59
$00-$38
$00-$59
3A
3
Minutes Alarm
0-59
$00-$38
$00-$59
3A
Hours
$01-$OC (AM) and $01-$12 (AM) and
(12 Hour Mode)
1-12
$81-$8C (PM)
$81-$92 (PM)
05
4
Hours
(24 Hour Mode)
0-23
$00-$17
$00-$23
05
Hours Alarm
$01-$OC (AM) and $01-$12 (AM) and
(12 Hour Mode)
1-12
$81-$8C (PM)
$81-$92 (PM)
05
5
Hours Alarm
(24 Hour Mode)
0-23
$00-$17
$00-23
05
Day of the Week
6 1-7
Sunday = 1
$01-$07
$01-$07
05
7
Date of the Month
1-31
$01-$1 F
$01-$31
OF
8
Month
1-12
$01-$OC
$01-$12
02
9
Year
0-99
$00-$63
$00-$99
4F
21
21
58
58
05
05
05
05
05
15
02
79
• Example: 5:58:21 Thursday 15 February 1979 (time isAM)
Static CMOS RAM
The 50 general purpose RAM bytes are not dedicated within
the CDP6818A. Theycan be used by the processor program,
and are fully available during the update cycle.
When time and calendar information must use battery back-
up very frequently there is other non-volatile data that must
be retained when main power is removed. The 50 user RAM
bytes serve the need for low-power CMOS battery-backed
storage, and extend the RAM available to the program.
When further CMOS RAM is needed, additional CDP6818As
may be included in the system. Thetime/calendarfunctions
may be disabled by holding the DVO-DV2 dividers, in
Register A, in the reset state by setting the SET bit in
Register B or by removing the oscillator. Holding the
dividers in reset prevents interrupts or saw output from
operating while setting the SET bit allows these functions to
occur. With the dividers clear, the available user RAM is
extended to 59 bytes. The high-order bit of the seconds
byte, bit 7 or Register A, and all bits of Register C and D
cannot effectively be used as general purpose RAM.
Interrupts
that interrupt to be initiated when the event occurs. A "0" in
the interrupt-enable bit prohibits the IRa pin from being
asserted due to the interrupt cause.
If an interrupt~ is already set when the interrupt becomes
enabled, the IRa pin is immediately activiated, though the
interrupt initiating the event may have occurred much
earlier. Thus, there are cases where the program should
clear such earlier initiated interrupts before first enabling
new interrupts.
When an interrupt event occurs, a flag bit is set to a "1" In
Register C. Each of the three interrupt sources have
separate flag bits in Register C, which are set independent
of the state of the corresponding enable bits in Register 8.
The flag bit may be used with or without enabling the
corresponding enable bits.
In the software scanned case, the program does not enable
the interrupt. The "interrupt" flag bit becomes a
which the software interrogates, when it wishes.
status
When
tbhit~
software detects that the flag is set, it is an indication to
software that the "interrupt" event occurred since the bit
was last read.
The RTC plus RAM includes three separate fully automatic
sources of interrupts to the processor. The alarm interrupt
may be programmed to occur at rates from once-per-
second to one-a-day. The periodic interrupt may be selected
for rates from half-a-second to 30.517 /.Is. The update-
ended interrupt may be used to indicate to the program that
an update cycle is completed. Each of these independent
interrupt conditions are described in greater detail in other
sections.
The processor program selects which interrupts, if any, it
wishes to receive. Three bits in Register 8 enable the three
interrupts. Writing a "1" to a interrupt-enable bit permits
However, there is one precaution. Theflag bits in Register C
are cleared (record of the interrupt event is erased) when
Register C is read. Double latching is included with Register
C so the bits which are set are stable throughout the read
cycle. All bits which are high when read by the program are
cleared, and new interrupts (on any bits) are held after the
read cycle. One, two or three flag bits may be found to be set
when Register C is used. The program should inspect all
utilized flag bits every time Register C Is read to insure that
no interru pts are lost.
The second flag bit usage method is with fully enabled
interrupts. When an interrupt-flag bit is set and the
590 __________________________________________________________

12 Page





SeitenGesamt 19 Seiten
PDF Download[ CDP6818A Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
CDP6818CMOS Real-Time ClockGE
GE
CDP6818CMOS Real Time ClockHarris Semiconductor
Harris Semiconductor
CDP6818ACMOS Real-Time ClockGE
GE
CDP6818ACMOS Real Time ClockHarris Semiconductor
Harris Semiconductor
CDP6818ACMOS Real Time ClockRCA Solid State
RCA Solid State

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche