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CDP68HC68P1 Schematic ( PDF Datasheet ) - GE

Teilenummer CDP68HC68P1
Beschreibung CMOS Single Port Input/Output
Hersteller GE
Logo GE Logo 




Gesamt 8 Seiten
CDP68HC68P1 Datasheet, Funktion
CMOS Peripherals
CDP68HC68P1
Advance Information
100
I D.
M ISO
MOS I
SCK
CE
DO
VSS
•• Voo
'5 D.
•• 02
13 03
" D'
" D'
.0 os
07
TOP VI EW
92C5-40410
TERMINAL ASSIGNMENT
CMOS Single Port Input/Output
Features:
• Fully static ope._ don
• 8-Bit I/O port - each bit can
• Operating voltage range 3-6 V
• Compatible with RCA/Motorola SPI bus
be individually programmed
as an input or output via an
• 2 external address pins tied to Voo or Vss
8-bit data direction register
to allow up to 4 devices to share the
• Programmable on-board
same chip enable
comparator
• Versatile bit-set and bit-clear capability
• Simultaneous transfer of
• Accepts either SCK clock polarity - SCK
compare information to CPU
voltage level is latched when chip enable
during read or write -
goes active
separate access not required
• All inputs are Schmitt- Trigger
The single port I/O is a serially addressed 8 bit Input/Output
port that allows byte or individual bit control. It consists of
three registers. an output buffer and control logic. Data is
shifted in and out of the port via a shift register that utilizes
the SPI (Serial.peripherallnterface) bus. The I/O port data
flow is controlled by the Data Direction Register and data is
stored in the Data Register that outputs or senses the logic
levels at the buffered 110 pins. All inputs. including the
serial interface are schmitt triggered. The device also
features a compare function that compares the data register
and port pin val ues for 4 programmable conditions and sets
a software accessible flag if the condition is satisfied. The
user also has the option of bit-set or bit-clear when writing
to the data register.
The CDP68HC66P1 is supplied in 16-lead, hermetiC. dual-
in-line side-brazed ceramic (D suffix). 16-lead dual-in-line
plastic (E suffix) and 16-lead, surface mount. (small outline),
plastic (M suffix) packages.
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE. (Voe)
(Voltage referenced to Vss terminal) .................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................................... -0.5 to Vee +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Pe):
For TA = -40 to +60°C (PACKAGE TYPE E) .............................................................. 500 mW
For TA = +60 to +85°C (PACKAGE TYPE E) ................................ Derate Linearly at 12 mW/oC to 200 mW
For TA = -55 to +100°C (PACKAGE TYPE D) ............................................................. 500 mW
For TA = +100 to 125°C (PACKAGE TYPE D) ............................... Derate Linearly at 12 mW/oC to 200 mW
For TA = -40 to HO°C (PACKAGE TYPE M)* ............................................................. 400 mW
For TA = +70 to +85°C (PACKAGE TYPE M)* ................................ Derate Linearly at 6 mW/oC to 310 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types) .................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ............................................................................... -55 to +125°C
PACKAGE TYPE E, M ............................................................................. -40 to +85°C
STORAGE-TEMPERATURE RANGE (Tatg) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 in. (1.59 ± 0.79 mm) from case for 10 s maximum .................................... +265°C
• Printed-circuit board mount: 57 mm x 57 mm minimum area x 1.6 mm thick G1 a epoxy glass. or equivalent.
File Number 1858
534 _________________________________________________________________






CDP68HC68P1 Datasheet, Funktion
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
coeC07 (101). (100): Chip-Identify bits
COS (RS): Register Select. When RS is low, the data
register is selected. When RS is high, the Direction Register
is selected.
C04 (if/W): Read/Write. Low when data is to be transferred
from the SPIIIO to the CPU (read) and high when the 110 is
receiving data from the CPU (write).
CDP68HC68P1
C03 (OF1). C02 (O!.O): Data Format Bits. These have
meaning only when R/W is high. During a write operation,
DF1 and DFO control how the byte following the control
word is interpreted. See "DATA FORMAT".
C01 (CM1). COO (CMO): Compare Mode Select. These bits
select one of four events which will setthe internal Condition
Flag. (See "COMPARE OPERATION")
Read Operation
During a read operation, the CPU transfers data from the
I/O by first sending a control byte on the MOSllinewhile the
chip-selected 1/0 sends compare information followed by
one or more data bytes on the MISO line.
~~~----------------------------.---------------~
MOSI
MISO Z
C07 C06 COS
0
C03 C02 COl coo
Z Z C07 C06 cos 0 C03
xxxxxxxx
8-BIT DATA WORD
x = DON'T CARE
Z ~ HIGH IMPEDANCE
* ~ COMPARE FLAG
Fig. 5 - Read bytes.
92CS - 40401
Write Opera,lon
The selected register will be continuously read if CE is held
low after the first data byte is shifted out.
During a write operation, the data byte follows the control
byte forthe selected register. While this byte is being shifted
in, old data from that register is shifted out. If CE remains
low after the data byte is shifted in, MISO becomes high
impedance and the new data is placed in the selected
register.
~~~----------------------------~----------------
MOSI
Misa z
C07 COs cos 1 C03 C02
Z Z C07 COS COS 1
COl COO
C03
8·BtT DATA WORD
PREVIOUS 8·81T WORO
Z' HIGH IMPEDANCE
* - COMPARE FLAG
92CS-40403
At the time the eighth data bit is strobed into the data pins
(00-07) will change as indicated in Fig. 7.
Fig. 6 - Write bytes.
I I I ...I IMOSI • ••
03
02 01
DO
SCK ••• ~ •••
00·07
PREVIOUS
I NEW
92CS-40402
Fig. 7 - Port-pin data changes.
Pin Description
100.101
Chip identify pins, normally tied to Voo or Vss. The 4
possible combinations of these pins allow 4 II0s to share a
common chip enable. When the levels at these pins match
those of the identify bits in the control word, the serial bus is
enabled. The chip identify pins will retain their previous
logiC state if the lines driving them become Hi-Z.
MISO
Master-in, Slave out pin. Data bytes are shifted out at this
pin most significant bit first. When the chip enable signal is
high, this pin is Hi-Z.
MOSI
Master-out, Slave in pin. Data bytes are shifted in at this pin
most significant bit first. This pin will retain its previous
logic state if its driving line becomes Hi-Z.
SCK
Serial clock input. This input causes serial data to be
latched from the MOSI input and shifted out on the MISO
output.
- _____________________________________________________________ 539

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