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PDF CDP65C51A Data sheet ( Hoja de datos )
| Número de pieza | CDP65C51A | |
| Descripción | CMOS Asynchronous Communications Interface Adapter | |
| Fabricantes | GE | |
| Logotipo |  |
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _CMOS Peripherals
Advance Information
TERMINAL ASSIGNMENT
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DTR
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8 21
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92CS-36774
CDP65C51A
CMOS Asynchronous Communications
Interface Adapter (ACIA)
Features:
• Compatible with 8-bit microprocessors
• Full duplex operation with buffered receiver and transmitter
• Data set/modem control functions
• Internal baud-rate generator with 15 programmable baud rates
(50 to 19,200)
• Program-selectable internally or externally controlled receiver rate
• Operates at baud rates up to 250,000 via proper crystal or clock selection
the RCA-CDP65C51A Asynchronous Communications
Interface Adapter (ACIA) provides an easily implemented,
program-controlled interface between 8-bit micro-
processor-based systems and serial communication data
sets and modems. The CDP65C51 A is identical to the RCA-
CDP65C51 except for the implementation of the CTS
function. If a not-clear-to-send signal is received during the
transmission of a character, the CDP65C51A will first allow
completion of that transmission, and then disable the
transmitter.
The CDP65C51 A has an internal baud-rate generator. This
feature eliminates the need for multiple component support
circuits, a crystal being the only other part required. The
Transmitter baud rate can be selected under program
control to be either 1 of 15 different rates from 50 to 19,200
baud, or 1/16 times an external clock rate. The Receiver
baud rate may be selected under program control to be
either the Transmitter rate, or at 1/16 times an external
clock rate. The CDP65C51A has programmable word
lengths of 5,6,7, or8 bits; even, odd, or no parity; 1,1 'h, or2
stop bits.
The CDP65C51A is designed for maximum programmed
control from the CPU, to simplify hardware implementation.
Three separate registers permit the CPU to easily select the
CDP65C51A operating modes and data-checking
parameters and determine operational status.
The Command Register controls parity, receiver echo
mode, transmitter interrupt control, the state of the RTS
line, receiver interrupt control, and the state of the DTR line.
• Programmable word lengths, number of stop bits, and
parity-bit generation and detection
• Programmable interrupt control
• Program reset
• Program-selectable serial echo mode
• Two chip selects
• 4 MHz, 2 MHz or 1 MHz operation (CDP65C51A-4,
CDP65C51A-2, CDP65C51A-1, respectively)
• Single 3 V to 6 V power supply
• Full TTL compatibility
• Synchronous CTS operation
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
The Status Register indicates the states of the IRQ, DSR,
and DCD lines, Transmitter and Receiver Data Registers,
and Overrun, Framing, and Parity Error conditions.
The Transmitter and Receiver Data Registers are used for
temporary data storage by the CDP65C51 A Transmit and
Receive circuits.
The CDP65C51A-1, CDP65C51A-2, and CDP65C51A-4 are
capable of Interfacing with microprocessors with cycle
times of 1 MHz, 2 MHz and 4 MHz, respectively.
The CDP65C51A is supplied in 28-lead, hermetic, dual-in-line
side brazed ceramiC packages (D suffix), in 28-lead, dual-in-
line plastiC packages (E suffix) and in 28-lead dual-In-Iine
smail-outline (SO) packages (M) suffix.
III
File Number 1928
- - - - - - - - - - - - - -_______________________________________________ 503
1 page  
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _CMOS Peripherals
CDP65C51A INTERNAL ORGANIZATION (Cont'd)
CDP65C51A
TIMING AND CONTROL
The Timing and Control logic controls the timing of data
transfers on the internal data bus and the registers, the Data
Bus Buffer, and the microprocessor data bus, and the
hardware reset features.
Timing is controlled by the system ¢2 clock input. The chip
will perform data transfers to or from the microcomputer
data bus during the ¢2 high period when selected.
All registers will be initialized by the Timing and Control
Logic when the Reset (RES) line goes low. Seethe individual
register description for the state of the registers following a
hardware reset.
TRANSMITTER AND RECEIVER
DATA REGISTERS
These registers are used as temporary data storage for the
CDP65C51A Transmit and Receive circuits. Both the
Transmitter and Receiver are selected by a Register Select 0
(RSO) and Register Select 1 (RS1) low condition. The
Read/Write line determines which actually uses the internal
data bus; the Transmitter Data Register is write only and the
Receiver Data Register is read only.
Bit 0 is the first bit to be transmitted from the Transmitter
Data Register (least significant bit first). The higher order
bits foHow in order. Unused bits in this register are "don't
care".
The Receiver Data Register holds the first received data bit
in bit 0 (least significant bit first). Unused high-order bits
are "0". Parity bits are not contained in the Receiver Data
Register. They are stripped off after being used for parity
checking.
STATUS REGISTER
Fig. 3 indicates the format of the CDP65C51A Status
Register. A description of each status bit follows.
76543210
I I I I I \I I I
L PARITY ERROR"
0- NO PARITY ERROR
1 - PARITY ERROR DETECTED
FRAMING ERROA"
a - NO FRAMING ERROR
1 - FRAMING ERROR DETECTED
' - - - OVERRUN"
0- NO OVERRUN
1 - OVERRUN HAS OCCURRED
RECEIVER DATA REGISTER FULL
0- NOT FULL
1 - FULL
TRANSMITTER DATA REGISTER EMPTY
0- NOT EMPTY
1 EMPTY
DATA CARRIER DETECT (DCo)
0- i5CB LOW (DETECT)
1 - i5CB HIGH (NOT DETECTED)
DATA seT READY d5SR)
0- DSR LOW (READY)
t - DSR HIGH (NOT READY)
INTERRUPT (IRQ)
O· NO INTERRUPT (fRO PIN HIGH)
1 - INTERRUFT HAS OCCURRED (ilm PIN LOW)
'NO INTERRUPTS OCCUR FOR
THESE CONDITIONS
Receiver Data Register Full (Bit 3)
This bit goes to a "1" when the CDP65C51A transfers data
from the Receiver Shift Register to the Receiver Data
Register, and goes to a "0" when the processor reads the
Receiver Data Register.
Transmitter Data Register Empty (Bit 4)
This bit goes to a "1" when the CDP65C51A transfers data
from the Transmitter Data Register to the Transmitter Shift
Register, and goes to a "0" when the processor writes new
data onto the Transmitter Data Register.
Data Carrier Detect (Bit 5) and
Data Set Ready (Bit 6)
These bits reflect the levels of the DCD and DSR inputs to
the CDP65C51 A. A "0" indicates a low level (true condition)
and a "1" indicates a high (false). Whenever either of these
inputs changes state, an immediate processor interrupt
occurs, unless the CDP65C51A is disabled (bit 0 of the
Command Register is a "0"). When the interrupt occurs, the
status bits will indicate the levels of the inputs immediately
after the change of state occurred. Subsequent level
changes will not affect the status bits until the Status
Register is interrogated by the processor. At that time,
another interrupt will immediately occur and the status bits
will reflect the new input levels.
.-
~
Framing Error (Bit 1), Overrun (Bit 2), and
Parity Error (Bit 0)
None of these bits causes a processor interrupt to occur,
but they are normally checked at the time the Receiver Data
Register is read so that the validity of the data can be
verified.
Interrupt (Bit 7)
This bit goes to a "0" when the Status Register has been
read by the processor, and goes to a "1" whenever any kind
of interrupt occurs.
CONTROL REGISTER
The Control Register selects the desired transmitter baud
rate, receiver clock source, word length, and the number of
stop bits.
Selected Baud Rate (Bits 0,1, 2, 3)
These bits, set by the processor, select the Transmitter
baud rate, which can be at 1/16 an external clock rate or one
of 15 other rates controlled by the internal baud rate
generator as shown in Fig. 4.
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A "0"
causes the Receiver to operate at a baud rate of 1/16 an
external clock. A "1" causes the Receiver to operate at the
same baud rate as is selected forthetransmitter asshown in
Fig. 4.
Word Length (Bits 5, 6)
These bits determine the word length to be used (5,6,7 or 8
bits). Fig. 4 shows the configuration for each number of bits
desired.
Fig. 3 - Status register format.
_________________________________________________________________ 507
5 Page 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _CMOS Peripherals
CDP65C51A OPERATION (Cont'd)
CDP65C51A
TRANSMITTER AND RECEIVER OPERATION (Cont'd)
Overrun In Echo Mode (Fig, 14)
If Overrun occurs In Echo Mode, the Receiver is affected the
same way as described in "Effect of Overrun on Receiver",
For the re-transmilted data, when overrun occurs, the TxD
line goes to the "MARK" condition until the first Start Bit
after the Receiver Data Register is read by the processor.
CHAR #n
~/r--------~I--------~,
CHAR #x
CHAR #x + 1
/r--------~I--------__,/r--------~I------
"'On rEEGSTOP
STOP
[%GI±J I
STOP
I
[BOI81J~~STOPI
GGT~H
I~
~
~
~
iRa LJIJ'
tJIJ 11 LllJ
lJlJrrT---
n EGIOTOP I
I [B00TTxO
START
PROCESSOR
INTERRUPT
FOR RECEIVER
DATA REGISTER
FULL
PROCESSOR
READS
STATUS
REGISTER
OVERRUN OCCURS
Tx o GOES TO
"MARK"
CONDITION
,/
PROCESSOR FINALLY
READS RECEIVER
DATA REGISTER,
LAST VALID
CHARACTER (#n)
PROCESSOR
iNTERRUPT
FORCHAR#x
IN RECEIVER
DATA REGISTER
92CM<~6788
Fig. 14 - Overrun in echo mode.
Framing Error (Fig, 15)
Framing Error is caused by the absence of Stop Bit(s) on
received data. The status bit is set when the processor
interrupt occurs. Subsequent data words are tested for
Framing Error separately, so the status bit will always
reflect the last data word received.
",0
(EXPECTED)
",0
(ACTUAL)
NOTES
1 FRAMING ERROR DOES NOT
INHIBIT RECEIVER OPERATION
2 IF NEXT DATA WORD IS OK
FRAMING ERROR IS CLEARED
I
PROCESSOR
INTERRUPT,
FRAMING
ERROR
BIT SET
92CM- 36789
Fig. 15 - Framing error.
___________________________________________________________________ 513
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CDP65C51A.PDF ] | |
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