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CDP6402 Schematic ( PDF Datasheet ) - GE

Teilenummer CDP6402
Beschreibung CMOS Universal Asynchronous Receiver/Transmitter
Hersteller GE
Logo GE Logo 




Gesamt 8 Seiten
CDP6402 Datasheet, Funktion
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP6402, CDP6402C
VDD TRC
NC 'PE
GND CLSI
RRD -
RBRe
CLS2
S8S
RBR7
PI
RBR6
CRL
RBR5
T8RS
RBR4
TBRl
RSR3
TeR6
ReR2
T8R5
RBR'
TBR4
PE TeR 3
FE TBR2
DE T8Rl
SFD TRO
RRC
~
TRE
TBRl
OR
RRI
TBRE
MR
TOP VIEW
92CS-34552
TERMINAL ASSIGNMENT
CMOS Universal Asynchronous
Receiver/Transmitter (UART)
Features:
• Low-power CMOS circuitry -
7.5 mW typo at 3.2 MHz
• Fully programmable with externally
selectable word length (5-8 bits),
(max. freq.) at VDD = 5 V
parity inhibit, even/odd parity, and
• Baud rate - DC to 200K bits/sec (max.)
I, 1.5,or 2 stop bits
at VDD = 5 V, 85°C
• Operating-temperature range:
DC to 400K bits/sec (max.)
(CDP6402D, CD) -55 to +125°
at VDD = 10 V,85°C
(CDP6402E, CE) -40 to +85° C
• 4 V to 10.5 operation
• AutomatIc data formatting and
• Replaces industry types IM6402
and HD6402
status generation
The RCA CDP6402 and CDP6402C are silicon-gate CMOS
Universal Asynchronous Receiver/Transmitter (UART)
circuits for interfacing computers or microprocessors to
asynchronous serial data channels. They are designed to
provide the necessary formatting and control for interfacing
between serial and parallel data channels. The receiver
converts serial start, data, parity, and stop bits to parallel
TRE +-r--------,
data verifying proper code transmission, parity and stop
bits. The transmitter converts parallel data into serial form
and automatically adds start parity and stop bits.
The data word can be 5, 6, 7 or 8 bits in length. Parity may be
odd, even or inhibited. Stop bits can be 1, 1.5, or 2 (when
transmitting 5-bit code).
III
TRC
L---------------j-+TRO
ClSI-~--+_-----+_--------~--~~--~----------------------------------------------_t-SBS
CLS2
EPE
CRL--r---t---------t---------~_ __.----~----------------------------------------------_t-Pl
MR
,-----------------------------------------~_+--4__RRI
SFD
DR OE TBRE
FE PE RBRe (MSBI
Fig. 1 - Functional block diagram.
~----------.;__ RRD
RBRI (LSB) 92CL-34553
File Number 1328
479






CDP6402 Datasheet, Funktion
CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP6402, CDP6402C
DYNAMIC ELECTRICAL CHARACTERISTICS al TA = -4010 +850 C. VDD ± 5%. Ir• If = 20 ns.
VIH = 0.7 VDD. VIL = 0.3 VDD. CL = 100 pF
CHARACTERISTIC t
Syslem Timing (See Fig. 6)
Minimum Pulse Width:
CRl
Minimum Setup Time
Control Word to CRl
Minimum Hold Time
Control Word after CRl
Propagation Delay Time
SFD High to SOD
SFD low to SOD
RRD High to Receiver Register
High Impedance
RRD low to Receiver Register
Active
Minimum Pulse Width:
MR
tCRl
tcwc
tccw
tSFDH
tSFDl
tRRDH
tRRDl
VDD
(V)
LIMITS
CDP6402
ITyp.-
Max.ll.
CDP6402C
Typ.-I Max.ll.
UNITS
- -5 50 150 50 150
10 40 100
5 20 50 20 50
10 0 40 -
-
-5 40 60 40 60
10 20 30 -
5
130 200 130
200
10 100 150 -
-
ns
5
130 200 130
200
10 40 60 -
-
5 80 150 80 150
10 40 70 -
-
5 80 150 80 150
10 40 70 -
-
- -5 200 400 200 400
10 100 200
-Typical values for TA = 250 C and nominal VDD·
ll.Maximum limits of minimum characteristics are the values above which all devices function.
t All measurements are made at the 50% POint of the transition except tri-state measurements
CONTROL INPUT WORD TIMING
CONTROL wORO------'r--------~~~~~~~~------------~Ir_--------
INPUT
CONTROL WORD BYTE
~----------tcwc
1" tccw
CRl _________~/~--------------~\~-------------
1.........- - - - - - tCRL
--I
SFO ------------......
RECEIVER REGI'HER DISCONNECT TIMING
R BUS 0
R BUS 7
900/0 700/0*
~- - - - - - -
I It RR0 H
-,
_........:_
_
10 %
___
_
_
__
_
__
_
_
_--ft_
_
_
_
_
_"""""""1---j
3 0/0
0
t RROL
RRO r-
R
------I
9<.CM - 38055
Fig. 6 - System timing waveforms.
484 ___________________________________________________________________

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