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CDP1877 Schematic ( PDF Datasheet ) - GE

Teilenummer CDP1877
Beschreibung Programmable Interrupt Controller
Hersteller GE
Logo GE Logo 




Gesamt 9 Seiten
CDP1877 Datasheet, Funktion
CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1877, CDP1877C
CASCAi5E
iR7
iRS
iRS
IR4
iR3
iRl!
iRi
iRO
TPA
TPB
MWR
MRD
VSS
I 28 VDD
2 27 8US7
3 26 8US6
4 25 BUS 5
5 24 8US4
6 23 8US 3
7 22 8US2
8 21 BUSI
9 20 BUSO
10 19 CS/Ax
II 18 CS/Ay
12 17 CS
13 16 cs
14 15 iNT
TOP VIEW
92CS-34371
TERMINAL ASSIGNMENT
Programmable Interrupt Controller (PIC)
Features:
• Compatible with CDP1800 series
• Programmable long branch vector address and vector interval
• 8 levels of interrupt per chip
Easily expandable
• Latched interrupt requests
• Hard wired interrupt priorities
• Memory mapped
• Multiple chip select inputs to minimize address space requirements
The RCA-COP1877 and CDP1877C. are programmable 8-
level interrupt controllers designed for use in CDP1800-
series microprocessor systems. They provide added
versatilty by extending the number of permissible interrupts
from 1 to N in increments of 8.
When a high to low transition occurs on any of the PIC
interrupt lines (IRO toTR'f). it will be latched and, unless the
request is masked, it will cause the INTERRUPT line on the
PIC and consequently the INTERRUPT input on the CPU to
go low.
The CPU accesses the PIC by having interrupt vector
register R(1) loaded with the memory address of the PIC.
Afterthe interrupt S3 cycle, this register value will appear at
the CPU address bus, causing the CPU to fetch an
instruction from the PIC. This fetch cycle clears the interrupt
request latch bit to accept a new high-to-Iow transition, and
also causes the PIC to issue a long branch instruction (CO)
followed by the preprogrammed vector address written into
the PIC's address registers, causing the CPU to branch to
the address corresponding to the highest priority active
interrupt request.
• Formerly RCA-Oev. Type No. TA10911 and TA10911C,
respectively.
If no other unmasked interrupts are pending, the
INTERRUPT output of the PIC will return high. When an
interupt is requested on a masked interrupt line, it will be
latched but it will not cause the PIC INTERRUPT output to
go low. All pending interrupts, masked and unmasked, will
be indicated by a "1" in the corresponding bit of the status
register. Reading of the status register will clear all pending
interrupt request latches.
Several PICs can be cascaded together by connecting the
INTERRUPT output of one chip to the CASCADE input of
another. Each cascaded PIC provides 8 additional interrupt
levels to the system. The number of units cascadable
depends on the amount of memory space and the extent of
the address decoding in the system.
Interrupts a~ioritized in descending order; IR7has the
highest and IRO has the lowest priority.
The COP1877 and CDP1877C are functionally identical.
They differ in that the COP1877 has a recommended
operating voltage range of4 to 10.5 volts, and the CDP1877C
has a recom mended operati ng voltage range of 4 to 6.5
volts. They types are supplied in 28-lead dual-in-line ceramic
packages (D suffix). and 28-lead dual-in-line plastic
packages (E suffix).
Programmable Interrupt Controller (PIC) Programming Model
WRITE ONLY
I ICONTROL REGISTER
B7 B6 B5 B4 B3 82 B1 eo WRITE ONLY
BUS 7
BUS 0
I IMASK REGISTER
M7 M6 M5 M4 M3 M2 M1 MO WRITE ONLY
BUS 7
BUS 0
STATUS REGISTER
I IS7 S6 S5 S4 S3 S2 S1 so READ ONLY
BUS 7
BUS 0
IP7
P6
POLLING REGISTER
P5 P4 P3 P2
P1
po ] READ ONLY
File Number 1319
430 _________________________________________________________________






CDP1877 Datasheet, Funktion
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _CMOS Peripherals
CDP1877, CDP1877C
Third (Low-Order Addre18) Byte.
INTERVAL 2
BUS 7
A7
I
AS
INTERVAL 4
BUS 7
AS
A4
A7
INTERVAL 8
BUS 7
AS
A7
INTERVAL 1b
BUS 7
AS
A7
AS
o
oo
Indicates active interrupt input number (binary 0 to 7).
BUSO
o
BUSO
oo
BUSO
oo
BUS 0
oo
..
Bits indicated by Ax (x=4 to 7) are the same as programmed
into the Control Register. All other bits are generated by the
PIC.
REGISTER ADDRESSES
In order to read/write or obtai n an interrupt vector from !!!y
PIC in the system, all chip selects (CS/Ax, CS/Ay, CS, CS)
must be valid during TPA.
CStAx and CStAy are multiplexed addresses; both must be
high during TPA, and set according to this table during TPB
to access the proper register.
CS/Ax
1
1
0
0
0
0
1
CS/Ay
0
0
1
0
0
1
1
RD
0
1
1
0
1
0
X
WR ACTION TAKEN
1 READ Long Branch instruction and vector for highest priority unmasked
interrupt pending.
0 WRITE to Page Register
0 WRITE to Control Register
1 READ Status Register
0 WRITE to Mask Register
1 READ Polling Register (Used to identify INTERRUPT source If Polling tech-
nique rather than INTERRUPT service Is used.)
X Unused condition
___________________________________________________________ 435

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