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CDP1854A Schematic ( PDF Datasheet ) - GE

Teilenummer CDP1854A
Beschreibung Programmable Universal Asynchronous Receiver/Transmitter
Hersteller GE
Logo GE Logo 




Gesamt 17 Seiten
CDP1854A Datasheet, Funktion
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Mode 1
Terminal Assignment
CMOS Peripherals
CDP1854A, CDP1854AC
Programmable Universal Asynchronous
Receiver/Transmitter (UART)
Features:
• Two operating modes:
• Baud rate-DC to 200 K bits/sec
Mode O-functionally compatible with
@ VDD=5 V
industry types such as the TR1602A
DC to 400 K bits/sec
Mode 1-interfaces directly with
@ VDD=10 V
CDP1800-series microprocessors • Fully programmable with externally se-
without additional components
lectable word length (5-8 bits), parity
• Full- or half-duplex operation
inhibit, even/odd parity, and 1, 1V" or
• Parity, framing, and overrun error
2 stop bits
detection
• False start bit detection
The RCA CDP1854A and CDP1854AC are silicon-gate
CMOS Universal Asynchronous Receiver/Transmitter
(UART) Circuits. They are designed to provide the necessary
formatting and control for interfacing between serial and
parallel data. For example, these UARTs can be used to
interface between a peripheral or terminal with serial I/O
ports and the 8-bit CDP1800-series microprocessor parallel
data bus system. The CDP1854A is capable of full duplex
operation, i.e., simultaneous conversion of serial input data
to parallel output data and parallel input data to serial
output data.
The CDP1854A UART can be programmed to operate in
one of two modes by using the mode control input. When
the mode input is high (MODE=1), the CDP1854A is
directly compatible with the CDP1800-series micro-
processor system without additional interface circuitry.
When the mode input is low (MODE=O), the device is
functionally compatible with industry standard UART's
such as the TR1602A. It is also pin compatible with these
types, except that pin 2 is used for the mode control input
instead of a VGG=-12 V supply connection.
The CDP1854A and the CDP1854AC are functionally
identical. The CDP1854A has a recommended operating-
voltage range of 4-10.5 volts, and the CDP1854AC has a
recommended operating-voltage range of 4-6.5 volts.
..
The CDP1854A and CDP1854AC are supplied in hermetic
40-lead dual-in-line ceramic packages (D suffix). in 40-lead
dual-in-line plastic packages (E suffix), and in 44-lead
plastic chip-carrier packages (0 suffix). The CDP1854AC is
also available in chip form (H suffix).
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VSS
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4
40 T CLOCK
39 EPE
38 WLS I
37 WLS 2
R BUS 7
5
36 SBS
R BUS 6
R BUS 5
6
7
35 PI
34 CRL
R BUS 4
R BUS 3
33 T BUS 7
32 T BUS 6
R BUS 2
10
31 T BUS 5
R BUS 1
R BUS 0
II
12
30 T BUS 4
29 T BUS 3
PE 13
28 T BUS 2
FE 14
27 T BUS I
OE 15
26 T8US 0
SFo
16
25 SOO
RCLOCK
iiJilj
17
18
24 TSRE
23 THlf[
oA 19
22 THRE
SOl 20
21 MR
TOP VIEW
* PIN 2 NO CONNECTION
ON CDP6402
92CS-2B456RI
Mode 0
Terminal Assignment
TERMINAL ASSIGNMENT
R BUSS
Raus 5
R 8US 4
R BUS3
R 8US 2
NC
R 8US1
39
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38
37
36
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T 8US 7
T8US6
T BUS 5
NC
T BUS4
M ~ T BUS3
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17
18
19 20 21
30
29
22 23 24 25 26 27 28
T BUS 2
T BUS 1
TSUSO
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44-Lead Plastic Chip-Carrier Package
(Q Suffix)
File Number1193
_______________________________________________________________ 387






CDP1854A Datasheet, Funktion
CMOS Peripherals - - - - - - - - - - - - - - - - - - - - - - - - - - -
CDP1854A, CDP1854AC
Oescrlptlon of Mode 1 Operation COP1800-Serles Micro-
processor Compatible (Mode Input=VOO)
1. Initialization and Controls
In the CDP1800-series microprocessor compatible mode,
the CDP1854A is configured to receive commands and
send status via the microprocessor data bus. The register
connected to the transmitter bus or the receiver bus is
determined by the RDIWR and RSEL inputs as follows:
Table III - Register Selection Summary
RSEL RO/WR
Function
Low
Low Load Transmitter Holding Register from
Transmitter Bus
Low High Read Receiver Holding Register from
Receiver Bus
High
Low Load Control Register from Transmitter
Bus
High High Read Status Register from Receiver Bus
One transmitter clock period after the Transmitter Shift
Register is loaded from the Transmitter Holding Register,
the THRE signal will go low and an interrupt will occur (INT
goes low). The next character to be transmitted can then be
loaded into the Transmitter Holding Register for trans-
mission with its start bit immediately following the last stop
bit of the prevIous character. This cycle can be repeated
until the last character is transmitted, at which time a final
THRE' TSRE interrupt will occur. This interrupt signals the
microprocessor that TR can be turned off. This is done by
reloading the original control byte in the Control Register
with the TR bit = 0, thus terminating the REQUEST TO
SEND (RTS) signal.
SERIAL DATA OUT (SDO) can be held low by setting the
BREAK bit in the Control Register (see Table IV). SDO is
held low until the BREAK bit is reset.
In this mode the CDP1854A is compatible with a bidirec-
tional bus system. The receiver and transmitter buses are
connected to the bus. CDP1800-series microprocessor 1/0
control output signals can be connected directly to the
CDP1854A inputs as shown in Fig. 2. The CLEAR input is
pulsed, resetting the Control, Status, and Receiver Holding
NO
NI
N2
MRO
VSS
0
0
VDD
RSEL
CS I
CS2
CS 3
RD/WR
RTS
m~
Registers and setting SERIAL DATA OUT (SDO) high. The
Control Register is loaded from the Transmitter Bus in
order to determine the operating configuration for the
UART. Data is transferred from the Transmitter Bus inputs
to the Control ~ister during TPB when the UART is
selected (CS1 . CS2' CS3::!l and the Control Register is
CPU
TPB
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TPB UART
CDPIB54A
TNT
EF,
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T'HRE
EFJ( -- - - - DA
I
designated (RSEL=H, RD/WR=L). The CDP1854A also has
a Status Register which can be read onto the Receiver Bus
(R BUS 0 - R BUS 7) in order to determine the status of the
UART. Some of these status bits are also available at
separate terminals as indicated in Table II.
2. Transmitter Operation
IT);
BUS
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"''0-- - -
FE
PEIOE
T BUS
SDI
SDO
CL:'EAR
R BUS
CLEii.R MODE
Before beginning to transmit, the TRANSMIT REQUEST
(TR) bit in the Control Register (see bit assignment, Table
IV) is set. Loading the Control Register with TR=1 (bit
7=high) inhibits changing the other control bits. Therefore
92CS-28460R!
two loads are required: one to format the UART, the second
to set TR. When TR has been set, a TRANSMITTER
HOLDING REGISTER EMPTY (THRE) interrupt will occur,
Fig. 2 - Recommended CDPl800-series connection,
Mode 1 (non-interrupt driven system).
signalling the microprocessor that the Transmitter Holding
Register is empty and may be loaded. Setting TR also
3, Receiver Operation
causes assertion of a low-level on the REQUEST TO SEND The receive operation begins when a start bit is detected at
(RTS) output to the peripheral. It is not necessary to set TR the SERIAL DATA IN (SDI) input. After detection of the first
for proper operation for the UART. If desired, it can be used high-to-Iow transition on the SDI line, a valid start bit is
to enable THRE interrupts and to generate the RTS signal. verified by checking for a lOW-level input 7-1/2 receiver
The Transmitter Holding Register is loaded from the bus by clock periods later. When a valid start bit has been verified,
TPB during execution of an oU..!E..!!t instruction. The the following data bits, parity bit (if programmed) and stop
CDP1854A is selected by CS1 . CS2 . CS3=1, and the bit(s) are shifted into the Receiver Shift Register by clock
Holding Register is selected by RSEL=L and RD/iiim=L.
When the CLEAR TO SEND (C'FSj input, which can be
pulse 7-112 In each bit time. The parity bit (if programmed)
is checked and receipt of a valid stop bit is verified. On
connected to a peripheral device output, goes low, the count 7-1/2 of the first stop bit, the received data is loaded
Transmitter Shift Register will be loaded from the Trans- into the Receiver Holding Register. If the word length is less
mitter Holding Register and data transmission will begin. If than 8 bits, zeros (low output level) are loaded into the
CTS is always low, the Transmitter Shift Register will be unused most significant bits. If DATA AVAILABLE (OA)
loaded on the first high-to-Iow edge of the clock which has not been reset by the time the Receiver Holding
occurs at least 1/2 clock period after the trailing edge of Register is loaded, the OVERRUN ERROR (OE) status bit is
TPB and transmission of a start bit will occur 1/2 clock set. One half clock period later, the PARITY ERROR (PE)
period later (see Fig. 3). Parity (if programmed) and stop and FRAMING ERROR (FE) status bits become valid for the
bit(s) will be transmitted following the last data bit. If the character in the Receiver Holding Register. At this time, the
word length selected is less than 8 bits, the most significant Data Available status bit is also set and the DATA
unused bits in the transmitter shift register will not be AVAILABLE (DA) and INTERRUPT (INT) outputs go low,
transmitted.
signalling the microprocessor that a received character is
392 _____________________________________________________________

6 Page









CDP1854A pdf, datenblatt
CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1854A, CDP1854AC
Functional Definitions for CDP1854A Terminals
Standard Mode 0
SIGNAL: FUNCTION
VDD:
Positive supply voltage.
MODE SELECT (MODE):
A low-level voltage at this input selects Standard Mode 0
Operation.
VSS:
Ground.
RECEIVER REGISTER DISCONNECT (RRD):
A high-level voltage applied to this input disconnects the
Receiver Holding Register from the Receiver Bus.
RECEIVER BUS (R BUS 7 - R BUS 0):
Receiver parallel data outputs.
PARITY ERROR (PE):
A high-level voltage at this output indicates that the
received parity does not compare to that programmed by
the EVEN PARITY ENABLE (EPE) control. This output is
updated each time a character is transferred to the Receiver
Holding Register. PE lines from a number of arrays can be
bused together since an output disconnect capability is
provided by the STATUS FLAG DISCONNECT (SFD) line.
FRAMING ERROR (FE):
A high-level voltage at this output indicates that the
received character has no valid stop bit, i.e., the bit
following the parity bit (if programmed) is not a high-level
voltage. This output is updated each time a character is
transferred to the Receiver Holding Register. FE lines from
a number of arrays can be bused together since an output
disconnect capability is provided by the STATUS FLAG
DISCONNECT (SFD) line.
OVERRUN ERROR (OE):
A high-level voltage at this output indicates that the DATA
AVAILABLE (DA) flag was not reset before the next
character was transferred to the Receiver Holding Register.
OE lines from a number of arrays can be bused together
since an output disconnect capability is provided by the
STATUS FLAG DISCONNECT (SFD) line.
STATUS FLAG DISCONNECT (SFD):
A high-level voltage applied to this input disables the 3-
state output drivers for PE, FE, OE, DA, and THRE, allowing
these status outputs to be bus connected.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
DATA AVAILABLE RESET (DAR):
A low-level voltage applied to this input resets the DA
flip-flop.
DATA AVAILABLE (DA):
A high-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
SERIAL DATA IN (SOl):
Serial data received at this input enters the receiver shift
register at a point determined by the character length. A
high-level voltage must be present when data is not being
received.
MASTER RESET (MR):
A high-level voltage at this input resets the Receiver
Holding Register, Control Register, and Status Register,
and sets the serial data output high.
TRANSMITTER HOLDING REGISTER EMPTY (THRE):
A high-level voltage at this output indicates that the
Transmitter Holding Register has transferred its contents
to the Transmitter Shift Register and may be reloaded with
a new character.
TRANSMITTER HOLDING REGISTER LOAD (THRL):
A low-level voltage applied to this input enters the character
on the bus into the Transmitter Holding Register. Data is
latched on the trailing edge of this signal.
TRANSMITTER SHIFT REGISTER EMPTY (TSRE):
A high-level voltage at this output indicates that the
Transmitter Shift Register has completed serial transmission
of a full character including stop bit(s). It remains at this
level until the start of transmission of the next character.
SERIAL DATA OUTPUT (SDO):
The contents of the Transmitter Shift Register (start bit,
data bits, parity bit, and stop bit(s» are serially shifted out
on this output. When no character is being transmitted, a
high-level is maintained. Start of transmission is defined as
the transition of the start bit from a high-level to a low-level
output voltage.
TRANSMITTER BUS (T BUS 0 - T BUS 7):
Transmitter parallel data inputs.
CONTROL REGISTER LOAD (CRL):
A high-level voltage at this input loads the Control Register
with the control bits (PI, EPE, SBS, WLS1, WLS2). This line
may be strobed or hardwired to a high-level input voltage.
PARITY INHIBIT (PI):
A high-level voltage at this input inhibits the parity genera-
tion and verification circuits and will clamp the PE output
low. If parity is inhibited the stop bit(s) will immediately
follow the last data bit on transmission.
STOP BIT SELECT (SBS):
This input selects the number of stop bits to be transmitted
after the parity bit. A high-level selects two stop bits, a
low-level selects one stop bit. Selection of two stop bits
with five data bits programmed selects 1.5 stop bits.
T CLOCK R CLOCK
PI
TPA~-"'-"",
SBS
WLSI
WLS2
THRL
EPE
UART
CoPI854A
i-------iTSRE
oA
SoI
soo
92CS-34506
Fig. 8 - Mode 0 connection diagram.
398 ___________________________________________________________

12 Page





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