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CDP680SG2C Schematic ( PDF Datasheet ) - GE

Teilenummer CDP680SG2C
Beschreibung CMOS High-Performance Silicon-Gate 8-Bit Microcomputer
Hersteller GE
Logo GE Logo 




Gesamt 22 Seiten
CDP680SG2C Datasheet, Funktion
_________________ 680S-Series Microprocessors and Microcomputers
Product Preview
CDP680SG2, CDP680SG2C
TERMINAL ASSIGNMENT
mn
TIfO
'eo",
,',".
''""
'''''''s""""""s ""'"""""""0
""""""""""""""""""""
'00
OSCI
om
TIMER
''''''''""""0"""0
'''''"'"""""".
TOP VIEW
CMOS High-Performance Silicon-Gate
a-Bit Microcomputer
Features:
• Typical full speed operating power
of 12 mWat5 V
• Typical WAIT mode power of 4 mW
• Typical STOP mode power of 5 /JW
• Fully static operation
• 112 bytes of on-chip RAM
• 2106 bytes 01 on-chip ROM
• 32 bidirectionalI/O lines
• High current drive'
• Internal B-bit timer with soltware
programmable 7-bit prescaler
• External timer input
• External and timer interrupts
• Self-check mode
• Master reset and power-on reset
• Single 3 to 6 volt supply
• On-chip oscillator with RC or crystal
mask options
• True bit manipulation
• Addressing modes with indexed
addressing for tables:
The CDP6805G2 Microcomputer Unit (MCU) belongs to
the CDP6805 Family of Microcomputers This 8-bit MCU
contains on-chip oscillator CPU, RAM, ROM, 1/0, and
Timer. The fully static design allows operation at frequencies
down to DC, further reducing its already low-power
consumption. It isa low-powerprocessordesigned for low-
end to mid-range applications in the consumer, automotive,
industrial, and communications markets where very low
power consumption constitutes an important factor.
-=-. .
TIMER
RESET NUM IRO
I3 2
Port
B
1/0
lines
PBO
PBI
PB2
PB3
PB4
PB5
PB6
PB7
Port
A
1/0
Lines
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
Port Data
B D"
Reg Reg
Port
A
Reg
Data
Dir
Reg
Accumulator
8A
Index
Register
8X
Condition
Code
Register CC
Stack
6 POinter
S
Program
Counter
High PCH
Program
Counter
8 low PCl
CPU
CPU
Control
AlU
Data
Dir
Reg
Port
C
Reg
Data
Dir
Reg
Port
D
Reg
PCO
PCI Pon
PC2 C
PC3 1/0
PC4 Lines
PC5
PC6
PC7
PDO
PDI
PD2
PD3
PD4
PD5
PD6
PD7
Port
D
1/0
Lines
198x8
Self· Check
ROM
Fig. 1 - CDP6805G2 CMOS microcomputer block diagram.
File Number 1364
------------___________________________________________________ 329






CDP680SG2C Datasheet, Funktion
6aOS-Serles Microprocessors and Microcomputers
CDP6805G2, CDP6805G2C
RSMAX
Co
~l
COSCl
COSC2
Rp
Q
1 MHz
400
5
0008
15-40
15-30
10
30
4 MHz
75
7
0012
15-30
15-25
10
40
Crystal Parameters
Units
0
pF
~F
pF
pF
MO
-
CDP6805G2
OSCl
OSC2
39 Rp
38
JCOSCl
"J COSC2
Crystal Oscillator Connections
L Cl Rs
~38
\
Co
38 101
39
Equivalent Crystal Circuit
(a)
R Unconnected
External Clock
(b) RC Oscillator Connecllon
Fig. 7 - Oscillator connections.
(c) External Clock Source Connections
10.
i4
!2
~I
1"- r--.
1"'-,
.::>
fil
It: 4
",-~
I-
2
. "jo.1
~
4
, .2
0.01
4 6 • 10 2 4 6 100 2 4 6 1000
RESISTANCE (kQ)
9lCS-38102
Fig. B - Typical frequency vs. resistance for RC oscillator option only.
334 ____________________________________________________________

6 Page









CDP680SG2C pdf, datenblatt
6805-Serles Microprocessors and Microcomputers _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP6805G2, CDP6805G2C
1~I(inCC)
007F-SP
O-DDRs
CLR IRQ Logic
TeR b7-0
TeR b6-1
Load PC From:
SWI: 1FFC/1FFD
1RU: 1FFA/1FFB
TIMER: 1FF8/1FF9
Timer Walt: 1FF6/1 FF7
Fig. 14 - i'iESfTand INTERRUPT processing flowchart.
TABLE 4 - INTERRUPT/INSTRUCTION EXECUTION PRIORITY AND VECTOR ADDRESS
(a) I Bit Set
Interrupt/Instruction
Priority
Vector
Address
---
RESET
SWI (or Other Instruction)
1
2
$1 FFE-$1 FFF
$1 FFC-$1 FFD
NOTE: IRQ and Timer Interrupts are not executed when the I bit is set; therefore, they
are not shown.
(b) I Bit Clear
Vector
Interrupt/Instruction
Priority
Address
RESET
IRQ
Timer
SWI (or other Instruction)
1
2
3
4
$1 FFE-$1 FFF
$1 FFA-$1 FFB
$1 FF8-$1 FF9
$1 FFS-$1 FF7"
$1 FFC-$1 FFD
• The Timer vector address from the WAIT mode is $1 FFS-$1 FF7.
340 _____________________________________________________________

12 Page





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