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CDP68HC05D2 Schematic ( PDF Datasheet ) - GE

Teilenummer CDP68HC05D2
Beschreibung HCMOS Microcomputers
Hersteller GE
Logo GE Logo 




Gesamt 30 Seiten
CDP68HC05D2 Datasheet, Funktion
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP68HC05D2
HCMOS Microcomputer
Introduction
General
The CDP68HC05D2 Microcomputer Unit (MCU) belongs to
the CDP6805 Family of Microcomputers This 8-bit MCU
contains on-chip oscillator CPU, RAM, ROM, 1/0, and
Timer The fully static design allows operation at frequen-
cies down to DC, further reducing its already low-power
consumption. It is a low-power processor designed for low-
end to mid-range applications in the telecommunications,
consumer, automotive, and industrial markets where very
low power consumption constitutes an Important factor.
The CDP68HC05D2 is supplied in a 40-lead hermetic dual-
in-line side brazed ceramic package (0 suffix), a 40-lead
dual-in-line plastic package (E suffix), and a 44-lead Plastic
Chip Carner (Q suffix).
Specific Features
• Typical power:
Operating, 25 mW
WAIT,7.5mW
STOP,5p.W
Fully static operation
96 bytes of on-chip RAM
2176 bytes of on-chip ROM
31110 lines
12 programmable open-dram output lines
On-chip oscillator for Timer
2.1 MHz internal operating frequency
Internal 16-bit timer
Serial Peripheral Interface (SPI)
External (~), timer, Port B, and Serial Interrupts
Self check mode
Single 2.5 to 6 volt supply (2-V data retention mode)
RC or crystal on-chip OSCillator
8x8 multiply Instruction
True bit manipulation
Indexed addreSSing for tables
Memory mapped 110
Functional Pin Descriptions
Voo and Vss
Power is supplied to the MCU using these two pins Vee is
power and V•• is ground.
N.C.
The pin labelled N.C. should be left disconnected.
III
IRQ (Maskable Interrupt Request)
IRQ IS a programmable option which provides two different
chOices of interrupt triggering sensitivity. These options
are. 1) negative edge-sensitive triggering only, or 2) both
negative edge-sensitive and level-sensitive triggering. In
the latter case, either type of input to the IRQ pin will pro-
duce the interrupt. The MCU completes the current instruc-
tion before it responds to the interrupt request. When the
IRQ pin goes low for at least onet'LlH, a logic one is latched
internally to Signify that an interrupt has been requested.
When the MCU completes its current instruction, the inter-
rupt latch is tested. If the interrupt latch contains a logic
one, and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU then begins the interrupt se-
quence. If the option is selected to include level-sensitive
triggering, then the IRQ input requires an external resistor
to Vee for "wire-OR" operation. See the INTERRUPTS sec-
tion for more detail.
RESET
The RESET input IS not required for startup but can be used
to reset the MCU internal state and provide an orderly soft-
ware startup procedure. Refer to the RESETs section for a
detailed description
TSM-204A
________________________________________________________________________________ 193






CDP68HC05D2 Datasheet, Funktion
680S-Serles Microprocessors and Microcomputers _________._______
CDP68HC05D2
$0000
liD
32 Bytes
0000
ports
8 Bytes
0000
Port A Data Register
Port B Data Register
Port C Data Register
$OOIF
$0020
User
ROM
128 Bytes
0031
0032
\
,
Unused
2 Bytes
Port 0 Data Register
Port A Data Direction Register
Port B Data Direction Register
Port C Data Direction Register
$009F
$ODA 0
0159
0160
RAM
96 Bytes
\
\
-- -i---$OOBF
$OOCO
Slack
0 191
0192
64 Bytes
SOOf-F
0255
$0100
0256
\
\
\
\
Senal Peripheral
Interface
3 Bytes
Unused
:; Bytes
-,-
TlmPf
10 Byles
Port 0 Data Direction Register
Unused
Unused
Serial Peripheral Control Register
Senal Peripheral Status Register
Serial Peripheral Data 110 Register
Unused
Unused
Unused
$08FF
$0900
User
ROM
2048 Bytes
Unused
5632 Bytes
2303
2304
\
\
\
\
Unused 2 Bytes
Special Port Control!
Stat Register
Unused
Unused
Unused
T,mp' Control Register
r---- Timer Status Register
nput Capture High Register
Input Capture low Register
$1 E:FF
$lF(X)
7935
7936
1 Byte
\
0031
Output Compare High Register
Output Compar;, LOW Register
Self Check
$lFDF f - - - - - -
$lFEO
Self· Check
Vectors
$1 FEF
$1 Ff-O
$lFFF
User
Vectors
16 Bytes
B175
8 176
8 191
256 Bytes
\
\
\
\
\
\
\
\
\
Counter High Register
Counter low Register
Alternate Counter High Register
Alternate Counter low Register
Unused
Unused
Special Port Contrrll/Stat Register
Unu',ed
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
lOA
SOB
SOC
SOD
SOE
SOF
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$lA
$1 B
$lC
$1D
$1 E
$1 F
Fig. 4 - Address Map
92CS-3811BR2
Table II - CDP68HC05D2 I/O Registers
ADDRESS
$0000-$001F
00 Port A Data
01 Port 8 Data
02 Port C Data
03 Port D Data
04 Port A DDA
05 Port 8 DDA
06 Port C DDR
07 Port D DDR
08 Unused
09 Unused
OA SPI Control
08 SPI Status
OC SPI Data
00 Unused
OE Unused
r-'
SPIE
SPIF
DATA
54
SPE DWOM MSTA CPOl
WCOl
MODF
CPHA
SPRI
OF Unused
• ;;:: dedicated as TeMP output
- = unused bits
SPRO
10 Unused
11 Unused
12 Timer Control
13 Timer Status
14 Capture High
15 Capture low
16 Compare High
'7 Compare low
18 Counter High
19 Counter low
1A Dual TM High
1B Dual TM low
lC Unused
10 Unused
1E Special Port
Cntl/STAT
IF Unused
DATA
7
ICIE OCIE
IGF OGF
PBIF
-
TOlE
TOF
EOE
EGG
IEDG OlVL
DLY PBIE PAOD
198 _______________________________________________________________

6 Page









CDP68HC05D2 pdf, datenblatt
6805-Serles Microprocessors and Microcomputers _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP68HC05D2
spaced far enough apart to be serviced. The minimum time
between pulses is a function of the number of cycles re-
quired to execute the interrupt service routine plus 21 cy-
cles. Once a pulse occurs, the next pulse should not occur
until the MCU software has exited the routine (an RTI oc-
curs). The second configuration shows several interrupt
fines "wlre-ORed" to form the interrupts at the processor.
Thus, if after servicing one interrupt the interrupt line re-
mains low, then the next interrupt is recognized.
Note: The Internal Interrupt latch IS cleared In the first part of the
service routine, therefore, one (and only one) external interrupt
pulse could be latched during t'UL and serviced as soon as the I bit is
cleared
CLEAR rna
REQUEST
LATCH
J,QAD PC FROM
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
PB: $1 FF2-$1 FF3
SPI: $1FF4-$1FFS
COMPLETE
INTERRUPT
ROUTINE
AND EXECUTE
RTI
92CM-39385
Fig. 9 - Hardware Interrupt Flowchart
204 _______________________________________________________________

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