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PDF CDP68HC05C8 Data sheet ( Hoja de datos )
| Número de pieza | CDP68HC05C8 | |
| Descripción | HCMOS Microcomputers | |
| Fabricantes | GE | |
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Series Microprocessors and Microcomputers
CDP68HCOSC4, CDP68HCOSC8
HCMOS Microcomputers
SECTION 1
INTRODUCTION
1.1 GENERAL
The CDP68HC05C4 HCMOS Microcomputer is a member of the CDP68HC05 Family of
low-cost single-chip microcomputers. This 8-bit microcomputer contains an on-chip
oscillator, CPU, RAM, ROM, 1/0, two serial interface systems, and timer. The fully static
design allows operation at frequencies down to dc, further reducing its already low-power
consumption.
The CDP68HC05C8 Microcomputer (MCU) device is similar to the CDP68HC05C4 MCU
with one exception. This exception incorporates 3584 additional bytes of user ROM for a
total of 7744 bytes of on-chip user ROM. All information on the CDP68HC05C4 MCU
applies to the CDP68HC05C8 MCU with the exception of the memory description.
1.2 FEATURES
The following are some of the hardware and software highlights of these HCMOS
Microcomputers.
HARDWARE FEATURES
• HCMOS Technology
• 8-Bit Architecture
• Power-Saving Stop and Wait Modes
• Fully Static Operation
• 176 Bytes of On-Chip RAM
• 4160 Bytes of On-Chip ROM (CDP68HC05C4)
7744 Bytes of On-Chip ROM (CDP68HC05C8)
• 24 Bidirectional 1/0 Lines
• 2.1-MHz Internal Operating Frequency at 5 Volts; 1 MHz at 3 Volts
• Internal 16-Bit Timer Similar to MC6801 Timer
• Serial Communications Interface System
• Serial Peripheral Interface System
• Self-Check Mode
• External, Timer, Serial Communications Interface, and Serial Peripheral Interface
Interrupts
• Master Reset and Power-On Reset
• Single 3- to 6-Volt Supply (2-V Data Retention Mode)
• On-Chip Oscillator with RC or Crystal Mask Options
• 40-Pin Dual-In-Line Package
• 44-Lead Plastic Chip Carrie~,Also Available
TSM·203A
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3
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP68HC05C4, CDP68HC05C8
2.1.6.3 Re. If the RC oscillator option is selected, then a resistor is connected to the
oscillator pins as shown in Figure 2-1 (d).
2.1.6.4 EXTERNAL CLOCK. An external clock should be applied to the OSCl Input with the OSC2
Input not connected, as shown in Figure 2-1 (e). An external clock may be used with either the RC or
crystal oscillator option. The toxov or tilCH specifications do not apply when uSing an external
clock input. The equivalent specification of the external clock source should be used In lieu of
toxov or tilCH
2.1.7 PAO-PA7
These eight 1/0 lines comprise port A. The state of any pin is software programmable and all port A
lines are configured as input during power-on or reset. Refer to INPUTIOUTPUT PROGRAMMING
paragraph below for a detailed description of 1/0 programming.
2.1.8 PBO-PB7
These eight lines comprise port B. The state of any pin is software programmable and all port B lines
are configured as input during power-on or reset. Refer to INPUTIOUTPUT PROGRAMMING
paragraph below for a detailed description of 1/0 programming.
III
2.1.9 PCO-PC7
These eight lines comprise port C. The state of any pin is software programmable and all port Clines
are configured as input during power-on or reset. Refer to INPUTIOUTPUT PROGRAMMING
paragraph below for a detailed description of 1/0 programming.
2.1.10 PDO-PD5, PD7
These seven lines comprise port D, a fixed input port that is enabled during power-on. All enabled
special functions (SPI and SCD affect the pins on this port. Four of these lines, PD2/MISO,
PD3/MOSI, PD4/SCK, and PD5/SS, are used in the serial peripheral interface (SPD discussed In
Section 6. Two of these lines, PDOI RDI and PDl ITDO, are used in the serial communications inter-
face (SCD discussed in Section 5. Refer to 2.2 INPUT/OUTPUT PROGRAMMING for a detailed
description of 1/0 programming.
__________________________________________________________________ 115
5 Page 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Series Microprocessors and Microcomputers
CDP68HCOSC4, CDP68HCOSC8
2.4.1 Accumulator (A)
The accumulator is an 8-bit general purpose register used to hold operands, results of the arithmetic
calculations, and data manipulations.
2.4.2 Index Register (X)
The X register is an 8-bit register which is used during the indexed modes of addressing. It provides
an 8-bit value which is used to create an effective address. The index register is also used for data
manipulations with the read-modify-write type of instructions and as a temporary storage register
when not performing addressing operations.
2.4.3 Program Counter (PC)
The program counter is a 13-bit register that contains the address of the next instruction to be
executed by the processor.
2.4.4 Stack Pointer (SP)
The stack pointer is a 13-bit register containing the address of the next free locations on the push-
down/pop-up stack. When accessing memory, the seven most significant bits are permanently
configured to 0000011. These seven bits are appended to the six least significant register bits to pro-
duce an address within the range of $ooFF to $OOCO. The stack area of RAM is used to store the
return address on subroutine calls and the machine state during Interrupts. During external or
power-on reset, and during a reset stack pointer (RS PI instruction, the stack pointer IS set to its up-
per limit ($ooFFI. Nested interrupt and/ or subroutines may use up to 64 (decimal) locations. When
the 64 locations are exceeded, the stack pointer wraps around and points to its upper limit ($OOFFI,
thus, losing the previously stored information. A subroutine call occupies two RAM bytes on the
stack, while an interrupt uses five RAM bytes.
III
2.4.5 Condition Code Register (CC)
The condition code register is a 5-bit register which indicates the results of the Instruction Just
executed as well as the state of the processor. These bits can be individually tested by a program
and specified action taken as a result of their state. Each bit is explained In the following
paragraphs.
2.4.5.1 HALF CARRY BIT (H). The H bit is set to a one when a carry occurs between bits 3 and 4 of
the ALU during an ADD or ADC instruction. The H bit is useful in binary coded deCimal
subroutines.
2.4.5.2 INTERRUPT MASK BIT (I). When the I bit is set, all interrupts are disabled. Clearing this bit
enables the interrupts. If an external interrupt occurs while the I bit is set, the interrupt is latched
and is processed after the I bit is next cleared; therefore, no interrupts are lost because of the I bit
being set. An internal interrupt can be lost if it is cleared while the I bit is set (refer to SECTION 4
PROGRAMMABLE TIMER, SECTION 5 SERIAL COMMUNICATIONS INTERFACE, and SECTION
6 SERIAL PERIPHERAL INTERFACE for more information).
______________________________________________________________ 121
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