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CD4724BMS Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CD4724BMS
Beschreibung CMOS 8-Bit Addressable Latch
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 10 Seiten
CD4724BMS Datasheet, Funktion
CD4724BMS
December 1992
CMOS 8-Bit Addressable Latch
Features
Pinout
• High Voltage Type (20V Rating)
• Serial Data Input
• Active Parallel Output
• Storage Register Capability
• Master Clear
• Can Function as Demultiplexer
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
VSS 8
CD4724BMS
TOP VIEW
16 VDD
15 RESET
14 WRITE DISABLE
13 DATA
12 Q7
11 Q6
10 Q5
9 Q4
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Multi-line Decoders
• A/D Converters
Description
CD4724BMS 8-bit addressable latch is a serial-input, parallel-
output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit is
addressed (by means of inputs A0, A1, A2) and when WRITE
DISABLE is at a low level. When WRITE DISABLE is high, data
entry is inhibited; however, all 8 outputs can be continuously
read independent of WRITE DISABLE and address inputs.
Functional Diagram
WRITE DISABLE
DATA
1
A0
2
A1
3
A2
DECODER
RESET
VDD = 16
VSS = 8
14
13
8
4
Q0
5
Q1
6
Q2
7
Q3
9
Q4
10
Q5
11 Q6
12 Q7
A master RESET input is available, which resets all bits to a
logic “0” level when RESET and WRITE DISABLE are at a high
level. When RESET is at a high level, and WRITE DISABLE is
at a low level, the latch acts as a 1-of-8 demultiplexer; the bit
that is addressed has an active output which follows that data
input, while all unaddressed bits are held to a logic “0” level.
The CD4724BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H1F
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1267
File Number 3348






CD4724BMS Datasheet, Funktion
Specifications CD4724BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 2
Note 1
OPEN
4 - 7, 9 - 12
GROUND
8
VDD
1 - 3, 13 - 16
9V ± -0.5V
50kHz
25kHz
Dynamic Burn-
In Note 1
-
1 - 3, 8
16
4 - 7, 9 - 12
14, 15
13
Irradiation
Note 2
4 - 7, 9 - 12
8 1 - 3, 13 - 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
*
A0 1
*
A1 2
*
A2 3
*
DATA 13
*
WRITE
DISABLE
14
*
RESET 15
VSS = 8
VDD = 16
A0
A1
A2
A0
A1
A2
A0 A0
A1
A2
A0
A0
A1
A1 A2
A1
A0
A1
A2
A2
A0
A1
A2 A2
A0
D
A1
A2
A0
A1
A2
WD
RR
ADDRESS
WD
VDD
DATA
D
WD
LATCH
0
4 Q0
R
D
WD
LATCH
1
5 Q1
R
D
WD
LATCH
2
6 Q2
R
D
WD
LATCH
3
7 Q3
R
D
WD
LATCH
4
9 Q4
R
D
WD
LATCH
5
10 Q5
R
D
WD
LATCH
6
11 Q6
R
D
WD
LATCH
7
12 Q7
R
p
n
Q
*ALL INPUTS ARE
PROTECTED BY
COS/MOS PROTECTION
NETWORK
VSS
p
n
FIGURE 1. LOGIC DIAGRAM OF CD4724BMS AND DETAIL OF 1 OF 8 LATCHES
7-1272

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