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ADF41020 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF41020
Beschreibung 18 GHz Microwave PLL Synthesizer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADF41020 Datasheet, Funktion
Data Sheet
18 GHz Microwave PLL Synthesizer
ADF41020
FEATURES
18 GHz maximum RF input frequency
Integrated SiGe prescaler
Software compatible with the ADF4106/ADF4107/ADF4108
family of PLLs
2.85 V to 3.15 V PLL power supply
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
4000 V HBM/1500 V CDM ESD performance
APPLICATIONS
Microwave point-to-point/multipoint radios
Wireless infrastructure
VSAT radios
Test equipment
Instrumentation
GENERAL DESCRIPTION
The ADF41020 frequency synthesizer can be used to implement
local oscillators as high as 18 GHz in the up conversion and
down conversion sections of wireless receivers and transmitters.
It consists of a low noise, digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, and high frequency programmable feedback dividers
(A, B, and P). A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). The synthesizer
can be used to drive external microwave VCOs via an active
loop filter. Its very high bandwidth means a frequency doubler
stage can be eliminated, simplifying system architecture and
reducing cost. The ADF41020 is software-compatible with the
existing ADF4106/ADF4107/ADF4108 family of devices from
Analog Devices, Inc. Their pinouts match very closely with
the exception of the ADF41020’s single-ended RF input pin,
meaning only a minor layout change is required when updating
current designs.
REFIN
AVDD DVDD
FUNCTIONAL BLOCK DIAGRAM
VP GND
R COUNTER
PHASE
FREQUENCY
DETECTOR
REFERENCE
RSET
CHARGE
PUMP
CP
CLK
DATA
LE
24-BIT INPUT
REGISTER
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
RFIN
3pF
50Ω
N = 4(BP + A)
DIVIDE
BY 4
P/P+ 1
A AND B
COUNTERS
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
AVDD
SDOUT
MUX
HIGH-Z
MUXOUT
M3 M2 M1
ADF41020
GND
CE
GND
Figure 1.
Rev. B
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
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ADF41020 Datasheet, Funktion
ADF41020
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
GND 1
GND 2
GND 3
RFIN 4
GND 5
ADF41020
TOP
VIEW
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 2, 3, 5, 9, 10 GND
Ground Pins.
4 RFIN Input to the RF Prescaler. This input is ac-coupled internally.
6, 7 AVDD Analog Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin. Pin 6 is the supply for the fixed divide-by-4 prescaler.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input
resistance of 100 kΩ (see Figure 9). This input can be driven from a TTL or CMOS crystal oscillator or it
can be ac-coupled.
11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high powers up the device, depending on the status of the power-down bit, PD1.
12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This is a high impedance CMOS input.
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high
impedance CMOS input.
14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches with the latch being selected using the control bits.
15 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
16, 17
DVDD
Digital Power Supply. This may range from 2.85 V to 3.15 V. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
18 VP Charge Pump Power Supply.
19 RSET Connecting a resistor between this pin and GND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
ICP MAX
=
25.5
RSET
So, with RSET = 5.1 kΩ, ICP MAX = 5.0 mA.
20 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the
external VCO.
EP Exposed Pad. The exposed pad must be connected to GND.
Rev. B | Page 6 of 16

6 Page









ADF41020 pdf, datenblatt
ADF41020
Data Sheet
PRESCALER
VALUE
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
MUXOUT
CONTROL
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)
PHASE DETECTOR
F2 POLARITY
0 NEGATIVE
1 POSITIVE
CHARGE PUMP
F3 OUTPUT
0 NORMAL
1 THREE-STATE
COUNTER
F1 OPERATION
0 NORMAL
1 R, A, B COUNTERS
HELD IN RESET
F4 F5
0X
10
11
FAST LOCK MODE
FAST LOCK DISABLED
FAST LOCK MODE 1
FAST LOCK MODE 2
TIMEOUT
M3
TC4
TC3
TC2
TC1
(PFD CYCLES)
0
00003
0
00017
0 0 1 0 11
0 0 1 1 15
0 1 0 0 19
0 1 0 1 23
0 1 1 0 27
0 1 1 1 31
0
0
1
1
1
1
1 0 0 0 35
1 0 0 1 39
1 0 1 0 43
1 0 1 1 47
1 1 0 0 51
1 1 0 1 55
1 1 1 0 59
1 1 1 1 63
M2
0
0
1
1
0
0
1
1
CPI6
CPI3
0
0
0
0
1
1
1
1
CPI5
CPI2
0
0
1
1
0
0
1
1
CPI4
CPI1
0
1
0
1
0
1
0
1
ICP (mA)
0.625
1.25
1.875
2.5
3.125
3.75
4.375
5.0
CE PIN
0
1
1
PD2
0
0
0
PD1
X
0
1
MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
SOFTWARE POWER-DOWN
P2 P1
00
01
10
11
PRESCALER VALUE
8/9
16/17
32/33
64/65
Figure 17. Function Latch Map
M1 OUTPUT
0 THREE-STATE OUTPUT
1 DIGITAL LOCK DETECT
(ACTIVE HIGH)
0 N DIVIDER OUTPUT
1 DVDD
0 R DIVIDER OUTPUT
1 RESERVED
0 SERIAL DATA OUTPUT
1 DGND
Rev. B | Page 12 of 16

12 Page





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