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PDF ADuCM360 Data sheet ( Hoja de datos )
| Número de pieza | ADuCM360 | |
| Descripción | Precision Analog Microcontroller | |
| Fabricantes | Analog Devices | |
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Data Sheet
Low Power, Precision Analog Microcontroller
with Dual Sigma-Delta ADCs, ARM Cortex-M3
ADuCM360/ADuCM361
FEATURES
Analog input/output
Dual 24-bit ADCs (ADuCM360)
Single 24-bit ADC (ADuCM361)
Programmable ADC output rate (3.5 Hz to 3.906 kHz)
Simultaneous 50 Hz/60 Hz noise rejection
At 50 SPS continuous conversion mode
At 16.67 SPS single conversion mode
Flexible input mux for input channel selection to both ADCs
Two 24-bit multichannel ADCs (ADC0 and ADC1)
6 differential or 12 single-ended input channels
4 internal channels for monitoring DAC, temperature
sensor, IOVDD/4, and AVDD/4 (ADC1 only)
Programmable gain (1 to 128)
RMS noise: 52 nV at 3.53 Hz, 200 nV at 50 Hz
Programmable sensor excitation current sources
On-chip precision voltage reference
Single 12-bit voltage output DAC
NPN mode for 4 mA to 20 mA loop applications
Microcontroller
ARM Cortex-M3 32-bit processor
Serial wire download and debug
Internal watch crystal for wake-up timer
16 MHz oscillator with 8-way programmable divider
Memory
128 kB Flash/EE memory, 8 kB SRAM
In-circuit debug/download via serial wire and UART
Power supply range: 1.8 V to 3.6 V (maximum)
Power consumption, MCU active mode
Core consumes 290 µA/MHz
Overall system current consumption of 1.0 mA with core
operating at 500 kHz (both ADCs on, input buffers off,
PGA gain of 4, one SPI port on, and all timers on)
Power consumption, power-down mode: 4 µA (wake-up
timer active)
On-chip peripherals
UART, I2C, and 2 × SPI serial I/O
16-bit PWM controller
19-pin multifunction GPIO port
2 general-purpose timers
Wake-up timer/watchdog timer
Multichannel DMA and interrupt controller
Package and temperature range
48-lead, 7 mm × 7 mm LFCSP
Specified for −40°C to +125°C operation
Development tools
Low cost QuickStart Development System
Third-party compiler and emulator tool support
Multiple functional safety features for improved diagnostics
APPLICATIONS
Industrial automation and process control
Intelligent precision sensing systems
4 mA to 20 mA loop-powered smart sensor systems
Medical devices, patient monitoring
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADuCM360/ADuCM361
DAC
AVDD
AGND
AIN0
AIN1
AIN2
AIN3
AIN4/IEXC
AIN5/IEXC
AIN6/IEXC
AIN7/VBIAS0/IEXC/
EXTREF2IN+
AIN8/EXTREF2IN–
AIN9/DACBUFF+
AIN10
AIN11/VBIAS1
VBIAS
GENERATOR
BUFFER
12-BIT
DAC
ON-CHIP
1.8V ANALOG
LDO
ON-CHIP
1.8V DIGITAL
LDO
POWER-ON
RESET
RESET
ARM
CORTEX-M3
PROCESSOR
16MHz
ON-CHIP
OSCILLATOR
(1% TYP)
16MHz
GPIO PORTS
UART PORTS
2 × SPI PORTS
I2C PORTS
XTALO
XTALI
MUX
VREF
AMP
BUF
MOD2
GAIN
Σ-Δ
MODULATOR
SINC2
FILTER
24-BIT
Σ-Δ ADC
SINC3/4
FILTER
MEMORY
128kB FLASH
8kB SRAM
TIMER0
TIMER1
WATCHDOG
WAKE-UP TIMER
PWM
DMA AND
INTERRUPT
CONTROLLER
SERIAL WIRE
DEBUG,
PROGRAMMING
AND DEBUG
19 GENERAL-
PURPOSE
I/O PORTS
IREF
DAC, TEMP,
IOVDD/4,
AVDD/4
CURRENT
SOURCES
SELECTABLE
VREF
SOURCES
PRECISION
REFERENCE
BUFFER
BUFFER
ADuCM361
SWDIO
SWCLK
DVDD_REG
AVDD_REG
GND_SW VREF– VREF+
INT_REF
Figure 2. ADuCM361 Functional Block Diagram
IOVDD
IOVDD
Rev. D | Page 5 of 24
5 Page 
Data Sheet
ADuCM360/ADuCM361
RMS NOISE RESOLUTION OF ADC0 AND ADC1
Internal Reference (1.2 V)
Table 2 through Table 5 provide rms noise specifications for ADC0 and ADC1 using the internal reference (1.2 V). Table 2 and Table 3 list
the rms noise for both ADCs with various gain and output update rate values. Table 4 and Table 5 list the typical output rms noise effective
number of bits (ENOB) in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown
in parentheses.) These results are taken with the input buffers off.
Table 2. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 1, 2, 4, 8, and 16
RMS Noise (µV)
Update
Rate (Hz)
Chop/Sinc
ADCFLT
Register
Value
Gain = 1,
±VREF,
ADCxMDE = 0x01
Gain = 2,
±500 mV,
ADCxMDE = 0x11
Gain = 4,
±250 mV,
ADCxMDE = 0x21
Gain = 8,
±125 mV,
ADCxMDE = 0x31
3.53
On/Sinc3 0x8E7C
1.05
0.45
0.23
0.135
30
Off/Sinc3 0x007E
2.1
1.37 0.63 0.37
50 Off/Sinc3 0x007D 3.7 1.6 0.83 0.47
100 Off/Sinc3 0x004D 5.45 2.41 1.13 0.63
488
Off/Sinc4 0x100F
10
4.7 2.2 1.3
976
Off/Sinc4 0x1007
13.5
6.5
3.3
1.7
1953
Off/Sinc4 0x1003
19.3
10
4.7 2.6
3906
Off/Sinc4 0x1001
67.0
36
16.6 8.8
Gain = 16,
±62.5 mV,
ADCxMDE = 0x41
0.072
0.22
0.29
0.38
0.79
1.1
1.55
4.9
Table 3. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 32, 64, and 128
RMS Noise (µV)
Update
Rate (Hz)
Chop/Sinc
ADCFLT
Register
Value
Gain = 32,1
±37.5 mV,
ADCxMDE =
0x49
Gain = 32,1, 2
±22.18 mV,
ADCxMDE =
0x51
Gain = 64,3
±18.75 mV,
ADCxMDE =
0x59
Gain = 64,3, 4
±10.3125 mV,
ADCxMDE =
0x61
Gain = 128,5
±9.375 mV,
ADCxMDE =
0x69
3.53
On/Sinc3 0x8E7C
0.067
0.064
0.073
0.055
0.058
30
Off/Sinc3 0x007E
0.202
0.2
0.196
0.16
0.174
50
Off/Sinc3 0x007D
0.24
0.24
0.25
0.21
0.21
100
Off/Sinc3 0x004D
0.35
0.32
0.36
0.27
0.31
488
Off/Sinc4 0x100F
0.7
0.67 0.71 0.58 0.62
976
Off/Sinc4 0x1007
0.99
0.91
1.01
0.74
0.83
1953
Off/Sinc4 0x1003
1.78
1.3
1.48 1.15 1.25
3906
Off/Sinc4 0x1001
6.44
2.68
3.59
1.4
2.2
Gain = 128,5, 6
±3.98 mV,
ADCxMDE =
0x71
0.052
0.155
0.2
0.25
0.57
0.7
1.0
1.4
1 ADCxMDE = 0x49 sets the PGA for a gain of 16 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x51 sets the PGA for a gain of 32 with the modulator gain off. ADCxMDE = 0x49 has slightly higher noise but supports a wider input range.
2 If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is ±17.5 mV.
3 ADCxMDE = 0x59 sets the PGA for a gain of 32 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x61 sets the PGA for a gain of 64 with the modulator gain off. ADCxMDE = 0x59 has slightly higher noise but supports a wider input range.
4 If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is ±8.715 mV.
5 ADCxMDE = 0x69 sets the PGA for a gain of 64 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the
modulator. ADCxMDE = 0x71 sets the PGA for a gain of 128 with the modulator gain off. ADCxMDE = 0x69 has slightly higher noise but supports a wider input range.
6 If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is ±3.828 mV.
Rev. D | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ADuCM360.PDF ] | |
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