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CD4532BMS Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CD4532BMS
Beschreibung CMOS 8-Bit Priority Encoder
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 9 Seiten
CD4532BMS Datasheet, Funktion
CD4532BMS
December 1992
CMOS 8-Bit Priority Encoder
Features
• High Voltage Type (20V Rating)
• Converts From 1 of 8 to Binary
• Provides Cascading Feature to Handle Any Number of
Inputs
• Group Select Indicates One or More Priority Inputs
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 0.5V at VDD = 5V
- 1.5V at VDD = 10V
- 1.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Priority Encoder
• Binary or BCD Encoder (Keyboard Encoding)
• Floating Point Arithmetic
Description
CD4532BMS consists of combinational logic that encodes
the highest priority input (D7 - D0) to a 3-bit binary code. The
eight inputs, D7 through D0, each have an assigned priority;
D7 is the highest priority and D0 is the lowest. The priority
encoder is inhibited when the chip-enable input E1 is low.
When E1 is high, the binary representation of the highest-
priority input appears on output lines Q2 - Q0, and the group
select line GS is high to indicate that priority inputs are
present. The enable-out (EO) is high when no priority inputs
are present. If any one input is high, EO is low and all cas-
caded lower-order stages are disabled.
The CD4532BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1E
H6W
Pinout
CD4532BMS
TOP VIEW
D4 1
D5 2
D6 3
D7 4
EI 5
Q2 6
Q1 7
VSS 8
16 VDD
15 E0
14 GS
13 D3
12 D2
11 D1
10 D0
9 Q0
Functional Diagram
D7
PRIORITY
SELECT
D0
ENCODER
E1
Q2
Q1
Q0
E0
GS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1227
File Number 3344






CD4532BMS Datasheet, Funktion
Logic Diagram
D1
* 11
D2
* 12
CD4532BMS
VDD
16
Q0
9
D3
* 13
D4
*1
D5
*2
D6
*3
D7
*4
D0
* 10
EI
*5
*ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VDD
Q1
7
Q2
6
GS
14
E0
15
VSS
8
VSS
FIGURE 1. CD4532BMS LOGIC DIAGRAM
TRUTH TABLE
INPUT
OUTPUT
E1 D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0
0XXXXXXXX0 0 0 0
1000000000000
1 1XXXXXXX1 1 1 1
1 0 1XXXXXX1 1 1 0
1 0 0 1XXXXX1 1 0 1
1 0 0 0 1XXXX1 1 0 0
1 0 0 0 0 1XXX1 0 1 1
1 0 0 0 0 0 1XX1 0 1 0
10000001X1001
1000000011000
X = Don’t Care
Logic 1 High
Logic 0 Low
E0
0
1
0
0
0
0
0
0
0
0
7-1232

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