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PDF CD4514BM Data sheet ( Hoja de datos )
| Número de pieza | CD4514BM | |
| Descripción | 4-Bit Latched/4-to-16 Line Decoders | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CD4514BM (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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February 1988
CD4514BM CD4514BC CD4515BM CD4515BC
4-Bit Latched 4-to-16 Line Decoders
General Description
The CD4514B and CD4515B are 4-to-16 line decoders with
latched inputs implemented with complementary MOS
(CMOS) circuits constructed with N- and P-channel en-
hancement mode transistors These circuits are primarily
used in decoding applications where low power dissipation
and or high noise immunity is required
The CD4514B (output active high option) presents a logical
‘‘1’’ at the selected output whereas the CD4515B presents
a logical ‘‘0’’ at the selected output The input latches are
R – S type flip-flops which hold the last input data presented
prior to the strobe transition from ‘‘1’’ to ‘‘0’’ This input data
is decoded and the corresponding output is activated An
output inhibit line is also available
Features
Y Wide supply voltage range
3 0V to 15V
Y High noise immunity
Y Low power TTL
0 45 VDD (typ )
fan out of 2
compatibility
driving 74L
Y Low quiescent power dissipation 0 025 mW package
Y Single supply operation
5 0 VDC
Y Input impedance e 1012X typically
Y Plug-in replacement for MC14514 MC14515
Logic and Connection Diagrams
Dual-In-Line Package
TL F 5994 – 1
Order Number CD4514B or CD4515B
Top View
TL F 5994 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 5994
RRD-B30M105 Printed in U S A
1 page  
Applications
Two CD4512 8-channel data selectors are used here with
the CD4514B 4-bit latch decoder to effect a complex data
routing system A total of 16 inputs from data registers are
selected and transferred via a TRI-STATE data bus to a
data distributor for rearrangement and entry into 16 output
registers In this way sequential data can be re-routed or
intermixed according to patterns determined by data select
and distribution inputs
Data is placed into the routing scheme via the 8 inputs on
both CD4512 data selectors One register is assigned to
each input The signals on A0 A1 and A2 choose 1-of-8
inputs for transfer out to the TRI-STATE data bus A fourth
signal labelled Dis disables one of the CD4512 selectors
assuring transfer of data from only one register
In addition to a choice of input registers 1–16 the rate of
transfer of the sequential information can also be varied
That is if the CD4512 were addressed at a rate that is
8 times faster than the shift frequency of the input registers
the most significant bit (MSB) from each register could be
selected for transfer to the data bus Therefore all of the
most significant bits from all of the registers can be trans-
ferred to the data bus before the next most significant bit is
presented for transfer by the input registers
Information from the TRI-STATE bus is redistributed by the
CD4514B 4-bit latch decoder Using the 4-bit address
INA – IND the information on the inhibit line can be trans-
ferred to the addressed output line to the desired output
registers A – P This distribution of data bits to the output
registers can be made in many complex patterns For exam-
ple all of the most significant bits from the input registers
can be routed into output register A all of the next most
significant bits into register B etc In this way horizontal
vertical or other methods of data slicing can be implement-
ed
TL F 5994 – 5
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CD4514BM.PDF ] | |
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