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CD4504BMS Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CD4504BMS
Beschreibung CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 8 Seiten
CD4504BMS Datasheet, Funktion
CD4504BMS
December 1992
CMOS Hex Voltage Level Shifter for
TTL-to-CMOS or CMOS-to-CMOS Operation
Features
Pinout
• High Voltage Type (20V Rating)
• Independence of Power Supply Sequence Consider-
ations
- VCC can Exceed VDD
- Input Signals can Exceed Both VCC and VDD
• Up and Down Level Shifting Capability
• Shiftable Input Threshold for Either CMOS or TTL
Compatibility
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
CD4504BMS
TOP VIEW
VCC 1
AOUT 2
AIN 3
BOUT 4
BIN 5
COUT 6
CIN 7
VSS 8
16 VDD
15 FOUT
14 FIN
13 SELECT
12 EOUT
11 EIN
10 DOUT
9 DIN
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
Description
CD4504BMS hex voltage level shifter consists of six circuits
which shift input signals from the VCC logic level to the VDD
logic level. To shift TTL signals to CMOS logic levels, the
SELECT input is at the VCC HIGH logic state. When the
SELECT input is at a LOW logic state, each circuit translates
signals from one CMOS level to another.
The CD4504BMS is supplied in these 16-lead outline packages:
Frit Seal DIP
H1F
Ceramic Flatpack H6W
VCC
* IN
(3, 5, 7, 9, 11, 14)
VDD
LEVEL
SHIFTER
OUT
(2, 4, 6, 10, 12, 15)
SELECT *
13
TTL/CMOS
MODE SELECT
VCC = PIN 1
VDD = PIN 16
VSS = PIN 8
VDD
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1140
File Number 3336






CD4504BMS Datasheet, Funktion
Specifications CD4504BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 2, 4, 6, 10, 12, 15 3, 5, 7-9, 11, 14
(Note 1)
16
1, 13
Static Burn-In 2 2, 4, 6, 10, 12, 15
(Note 1)
8
16 1, 3, 5, 7, 9, 11,
13, 14
Dynamic Burn-
In (Note 1, 3)
-
8 16 1, 2, 4, 6, 10, 12, 3, 5, 7, 9, 11, 14
15
Irradiation
(Note 2)
2, 4, 6, 10, 12, 15
8 1, 3, 5, 7, 9, 11, 13,
14, 16
NOTES:
1. Each pin except VCC, VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VCC, VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
3. Oscillator output to be VDD/2.
7-1145

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