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AD7170 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7170
Beschreibung 12-Bit Low Power Sigma-Delta ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 15 Seiten
AD7170 Datasheet, Funktion
Data Sheet
FEATURES
Output data rate: 125 Hz
Pin-programmable power-down and reset
Status function
Internal clock oscillator
Current: 135 µA
Power supply: 2.7 V to 5.25 V
−40°C to +105°C temperature range
Package: 10-lead, 3 mm × 3 mm LFCSP
INTERFACE
2-wire serial (read-only device)
SPI compatible
Schmitt trigger on SCLK
APPLICATIONS
Pressure measurement
Industrial process control
Portable instrumentation
12-Bit Low Power Sigma-Delta ADC
AD7170
FUNCTIONAL BLOCK DIAGRAM
GND VDD
REFIN(+) REFIN(–)
AIN(+)
AIN(–)
12-BIT Σ-Δ
ADC
DOUT/RDY
SCLK
AD7170
INTERNAL
CLOCK
PDRST
Table 1.
VREF = VDD
5V
3V
Figure 1.
RMS Noise
11.5 μV
6.9 μV
P-P Noise
76 μV
45 μV
P-P
Resolution
12 bits
12 bits
ENOB
12 bits
12 bits
GENERAL DESCRIPTION
The AD7170 is a very low power 12-bit analog-to-digital converter
(ADC). It contains a precision 12-bit sigma-delta (Σ-Δ) ADC
and an on-chip oscillator. Consuming only 135 μA, the AD7170
is particularly suitable for portable or battery operated products
where very low power is a requirement. The AD7170 also has a
power-down mode in which the device consumes 5 μA, thus
increasing the battery life of the product.
For ease-of-use, all the features of the AD7170 are controlled by
dedicated pins. Each time a data read occurs, eight status bits
are appended to the 12-bit conversion. These status bits contain
a pattern sequence that can be used to confirm the validity of
the serial transfer.
The output data rate of the AD7170 is 125 Hz, whereas the
settling time is 24 ms. The AD7170 has one differential input
and a gain of 1. This is useful in applications where the user
needs to use an external amplifier to implement system-specific
filtering or gain requirements.
The AD7170 operates with a power supply from 2.7 V to 5.25 V.
It is available in a 10-lead LFCSP package.
The AD7171 is a 16-bit version of the AD7170. It has the same
feature set as the AD7170 and is pin-for-pin compatible.
Rev. B
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AD7170 Datasheet, Funktion
Data Sheet
AD7170
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.
Table 2.
Parameter1, 2
READ
t1
t2
t3 3
t4
RESET
t5
t6
Limit at TMIN, TMAX
100
100
0
60
80
10
100
25
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ms typ
Conditions/Comments
SCLK high pulse width
SCLK low pulse width
SCLK active edge to data valid delay4
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK inactive edge to DOUT/RDY high
PDRST low pulse width
PDRST high to data valid delay
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 3.
3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is the falling edge of SCLK.
TIMING DIAGRAMS
ISINK (1.6mA WITH VDD = 5V,
100µA WITH VDD = 3V)
TO
OUTPUT
PIN
50pF
1.6V
ISOURCE (200µA WITH VDD = 5V,
100µA WITH VDD = 3V)
Figure 2. Load Circuit for Timing Characterization
DOUT/RDY (O)
SCLK (I)
MSB
t3
t1
LSB
t4
I = INPUT, O = OUTPUT
t2
Figure 3. Read Cycle Timing Diagram
PDRST (I)
t5
DOUT/RDY (O)
t6
I = INPUT, O = OUTPUT
Figure 4. Resetting the AD7170
Rev. B | Page 5 of 14

6 Page









AD7170 pdf, datenblatt
Data Sheet
DATA OUTPUT CODING
The AD7170 uses offset binary coding. Therefore, a negative
full-scale voltage results in a code of 000...000, a zero differential
input voltage results in a code of 100...000, and a positive full-
scale input voltage results in a code of 111...111. The output
code for any analog input voltage can be represented as
Code = 2N – 1 × [(VINx/VREF) + 1]
where:
VINx is the analog input voltage.
N = 12 for the AD7170.
REFERENCE
The AD7170 has a fully differential input capability for the
channel. The common-mode range for these differential inputs
is GND to VDD. The reference input is unbuffered; therefore,
excessive R-C source impedances introduce gain errors. The
reference voltage REFIN (REFIN(+) − REFIN(−)) is VDD
nominal, but the AD7170 is functional with reference voltages
of 0.5 V to VDD. In applications where the excitation (voltage or
current) for the transducer on the analog input also drives the
reference voltage for the part, the effect of the low frequency
noise in the excitation source is removed because the application
is ratiometric. If the AD7170 is used in a nonratiometric
application, a low noise reference should be used.
Recommended 2.5 V reference voltage sources for the AD7170
include the ADR381 and ADR391, which are low noise, low
power references. Also, note that the reference inputs provide
a high impedance, dynamic load. Because the input impedance
of each reference input is dynamic, resistor/capacitor combinations
on these inputs can cause dc gain errors, depending on the output
impedance of the source that is driving the reference inputs.
Reference voltage sources such as those recommended above
(the ADR391, for example) typically have low output
impedances and are, therefore, tolerant to decoupling capacitors
on REFIN(+) without introducing gain errors in the system.
Deriving the reference input voltage across an external resistor
means that the reference input sees a significant external source
impedance. External decoupling on the REFIN(±) pins is not
recommended in this type of circuit configuration.
DIGITAL INTERFACE
The serial interface of the AD7170 consists of two signals: SCLK
and DOUT/RDY. SCLK is the serial clock input for the device,
and data transfers occur with respect to the SCLK signal. The
AD7170
DOUT/RDY pin is dual purpose: it functions as a data ready
pin and as a data out pin. DOUT/RDY goes low when a new
data-word is available in the output register. A 24-bit word is
placed on the DOUT/RDY pin when sufficient SCLK pulses are
applied. This consists of a 12-bit conversion result followed by
four 0s to generate a 16-bit word. Following this, eight status
bits are output. Table 8 shows the functions of the status bits.
RDY: ready bit. This bit is set low to indicate that a conversion
is available.
0: This bit is set to 0.
ERR: This bit is set to 1 if an error occurred during the conver-
sion. An error occurs when the analog input is outside range.
ID1, ID0: ID bits. These bits indicate the ID number for the
AD7170. Bit ID1 and Bit ID0 are set to 0 for the AD7170.
PAT2, PAT1, PAT0: status pattern bits. They are set to 101 by
default. When the user reads the data from the AD7170, a
pattern check can be performed. If the PAT2 to PAT0 bits are
different from their default values, the serial transfer from the
ADC was not performed correctly.
Table 8. Status Bits
RDY 0 ERR ID1
ID0
PAT2
PAT1
PAT0
DOUT/RDY is reset high when the conversion is read. If the
conversion is not read, DOUT/RDY goes high prior to the data
register update to indicate when not to read from the device.
This ensures that a read operation is not attempted while the
register is being updated. Each conversion can be read only
once. The data register is updated for every conversion. So,
when a conversion is complete, the serial interface is reset, and
the new conversion is placed in the data register. Therefore, the
user must ensure that the complete word is read before the next
conversion is complete.
When PDRST is low, the DOUT/RDY pin is tristated. When
PDRST is taken high, the internal clock requires 1 ms, approx-
imately, to power up. Following this, the ADC continuously
converts. The first conversion requires the complete settling
time (see Figure 4). DOUT/RDY goes high when PDRST is
taken high and returns low only when a conversion is available.
The ADC then converts continuously, subsequent conversions
being available at 125 Hz. Figure 3 shows the timing for a read
operation from the AD7170.
Rev. B | Page 11 of 14

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