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CD4502BMS Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer CD4502BMS
Beschreibung CMOS Strobed Hex Inverter/Buffer
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 8 Seiten
CD4502BMS Datasheet, Funktion
CD4502BMS
December 1992
CMOS Strobed Hex Inverter/Buffer
Features
Pinout
• High Voltage Type (20V Rating)
• 2 TTL Load Output Drive Capability
CD4502BMS
TOP VIEW
• 3 State Outputs
• Common Output Disable Control
• Inhibit Control
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
D3 1
Q3 2
D1 3
3 STATE
OUTPUT DISABLE
4
Q1 5
D2 6
Q2 7
VSS 8
16 VDD
15 D6
14 Q6
13 D5
12 INHIBIT
11 Q5
10 D4
9 Q4
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Functional Diagram
• 3 State Hex Inverter for Interfacing ICs with Data
Buses
• COS/MOS to TTL Hex Buffer
Description
CD4502BMS consists of six inverter/buffers with 3 state
outputs. A logic “1” on the OUTPUT DISABLE input
produces a high impedance state in all six outputs. This
feature permits common busing of the outputs, thus
simplifying system design. A Logic “1” on the INHIBIT input
switches all six outputs to logic “0” if the OUTPUT DISABLE
input is a logic “0”. This device is capable of driving two
standard TTL loads, which is equivalent to six times the
JEDEC “B” series IOL standard.
3 STATE 4
OUTPUT DISABLE
INHIBIT 12
D1 3
D2 6
D3 1
D4 10
D5 13
D6 15
5 Q1
7 Q2
2 Q3
9 Q4
11 Q5
14 Q6
The CD4502BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1F
H6W
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-473
File Number 3334






CD4502BMS Datasheet, Funktion
Specifications CD4502BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 2, 5, 7, 9, 11, 14 1, 3, 4, 6, 8, 10, 12,
Note 1
13, 15
16
Static Burn-In 2 2, 5, 7, 9, 11, 14 8 1, 3, 4, 6, 10, 12,
Note 1
13, 15, 16
Dynamic Burn-
In Note 1
-
8
16 2, 5, 7, 9, 11, 14
4 1, 3, 6, 10, 12, 13,
15
Irradiation
2, 5, 7, 9, 11, 14
8
1, 3, 4, 6, 10, 12,
Note 2
13, 15, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
DI *
3-STATE
OUTPUT
*
DISABLE
INHIBIT *
INVERTER/BUFFER NO. 1
VDD
Q1
TO 5 OTHER
INVERTER/BUFFERS
VSS
VDD
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
TRUTH TABLE
DISABLE INHIBIT
Dn
0 00
0 01
0 1X
1 XX
Logic 0 = Low
Logic 1 = High
Z = High Impedance
X = Don’t Care
FIGURE 1. LOGIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTER/BUFFERS
Qn
1
0
0
Z
Test Circuit and Waveform
PULSE
GENERATOR
D3
Q3
D1
DISABLE
Q1
D2
Q2
VSS
1
2
3
4
5
6
7
8
16 VDD
15 D6
14 Q6
13 D5
12 INHIBIT
11 Q5
10 D4
9 Q4
TEST CONDITIONS
TEST PIN 15 POINT A
tPHZ VSS
VSS
tPLZ VDD
VDD
tPZL VDD
VDD
tPZH VSS
VSS
VDD
0.01kµF
1k
CL
A
50%
tPLZ
tPHZ
10%
90%
50%
tPZL
90%
10%
tPZH
VDD
VOL
VOH
VSS
FIGURE 2. DISABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS
7-478

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