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Teilenummer | EDD1232ABBH |
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Beschreibung | 128M bits DDR SDRAM | |
Hersteller | Elpida Memory | |
Logo | ||
Gesamt 30 Seiten DATA SHEET
128M bits DDR SDRAM
EDD1232ABBH (4M words × 32 bits)
Specifications
• Density: 128M bits
• Organization
⎯ 1M words × 32 bits × 4 banks
• Package: 144-ball FBGA
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 2.5V ± 0.125V
• Data rate: 400Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
⎯ Sequential (2, 4, 8)
⎯ Interleave (2, 4, 8)
• /CAS Latency (CL): 3
• Precharge: auto precharge operation for each burst
access
• Driver strength: weak/matched
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 4096 cycles/32ms
⎯ Average refresh period: 7.8μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
Features
• ×32 organization
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
Document No. E0874E40 (Ver. 4.0)
Date Published April 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2006-2007
EDD1232ABBH
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.125V, VSS, VSSQ = 0V)
Parameter
Symbol Grade
max.
Unit Test condition
Operating current (ACT-PRE) IDD0
Operating current
(ACT-READ-PRE)
Idle power down standby
current
IDD1
IDD2P
Floating idle standby current IDD2F
Quiet idle standby current IDD2Q
Active power down standby
current
IDD3P
Active standby current
IDD3N
Operating current
(Burst read operation)
Operating current
(Burst write operation)
IDD4R
IDD4W
Auto Refresh current
IDD5
Self refresh current
Operating current
(4 banks interleaving)
IDD6
IDD7A
140
mA
CKE ≥ VIH,
tRC = tRC (min.)
160
mA
CKE ≥ VIH, BL = 4,CL = 3,
tRC = tRC (min.)
20 mA CKE ≤ VIL
40
mA
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
35
mA
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
40 mA CKE ≤ VIL
100
mA
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
330 mA CKE ≥ VIH, BL = 2, CL = 3
330 mA CKE ≥ VIH, BL = 2,CL = 3
200
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
7
mA
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
380 mA BL = 4
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.125V, VSS, VSSQ = 0V)
Parameter
Input leakage current
Output leakage current
Symbol
ILI
ILO
min.
–2
–5
max.
2
5
Unit Test condition
µA VDD ≥ VIN ≥ VSS
µA VDDQ ≥ VOUT ≥ VSS
Notes
1, 2, 9
1, 2, 5
4
4, 5
4, 10
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
1, 5, 6, 7
Notes
Data Sheet E0874E40 (Ver. 4.0)
6
6 Page EDD1232ABBH
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is Low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A11 (input pins)
Row address (AX0 to AX11) is determined by the A0 to the A11 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A7 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle. This
column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A11)
Part number
Row address
Column address
EDD1232ABBH
AX0 to AX11
AY0 to AY7
A8 (AP) (input pin)
A8 defines the precharge mode when a precharge command, a read command or a write command is issued. If A8
= high when a precharge command is issued, all banks are precharged. If A8 = Low when a precharge command is
issued, only the bank that is selected by BA1/BA0 is precharged. If A8 = high when read or write command, auto-
precharge function is enabled. While A8 = Low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Data Sheet E0874E40 (Ver. 4.0)
12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ EDD1232ABBH Schematic.PDF ] |
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