PDF EDD1204ALTA Data sheet ( Hoja de datos )

Número de pieza	EDD1204ALTA
Descripción	128 M-bit Synchronous DRAM
Fabricantes	Elpida Memory
Logotipo
Hay una vista previa y un enlace de descarga de EDD1204ALTA (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The EDD1204ALTA, EDD1208ALTA, EDD1216ALTA are high-speed 134,217,728 bits synchronous dynamic random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V). The synchronous DRAM is packaged in 66-pin Plastic TSOP (II). Features • Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge • Double Data Rate interface Differential CLK (/CLK) input Data inputs and DM are synchronized with both edges of DQS Data outputs and DQS are synchronized with a cross point of CLK and /CLK • Quad internal banks operation • Possible to assert random column address in every clock cycle • Programmable Mode register set /CAS latency (2, 2.5) Burst length (2, 4, 8) Wrap sequence (Sequential / Interleave) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • x4, x8, x16 organization • Byte write control (x4, x8) by DM • Byte write control (x16) by LDM and UDM • 2.5 V ± 0.2 V Power supply for VDD • 2.5 V ± 0.2 V Power supply for VDDQ • Maximum clock frequency up to 133 MHz • SSTL_2 compatible with all signals • 4,096 refresh cycles/64 ms • 66-pin Plastic TSOP (II) (10.16 mm (400)) • Burst termination by Precharge command and Burst stop command The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0136E30 (Ver. 3.0) Date Published October 2001 (K) Printed in Japan Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. 1 page EDD1204ALTA, EDD1208ALTA, EDD1216ALTA VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD [EDD1208ALTA] 66-pin Plastic TSOP (II) (10.16 mm (400)) 4M word x 8 bit x 4 bank 1 66 2 65 3 64 4 63 5 62 6 61 7 60 8 59 9 58 10 57 11 56 12 55 13 54 14 53 15 52 16 51 17 50 18 49 19 48 20 47 21 46 22 45 23 44 24 43 25 42 26 41 27 40 28 39 29 38 30 37 31 36 32 35 33 34 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS A0 - A11 A0 - A11 A0 - A9 BA0, BA1 DQ0 - DQ7 DQS CLK, /CLK CKE /CS /RAS : Address inputs : Row address inputs : Column address inputs : Bank select : Data inputs/outputs : Data strobe : System clock input : Clock enable : Chip select : Row address strobe /CAS /WE DM VDD VSS VDDQ VSSQ VREF NC : Column address strobe : Write enable : DQ write mask enable : Supply voltage : Ground : Supply voltage for DQ and DQS : Ground for DQ and DQS : Input reference : No connection Preliminary Data Sheet E0136E30 5 5 Page EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 2. Commands Extended mode register set command (/CS, /RAS, /CAS, /WE Low) Fig.1 Extended mode register set command The EDD12xxALTA has an extended mode register that defines enabling or disabling DLL. In this command, A0 through A11, BA0 and BA1 are the data input pins. After power on, the extended mode register set command must be executed for enabling or disabling DLL. The extended mode register can be set only when all banks are in idle state. During tMRD, the EDD12xxALTA can not accept any other commands. CLK CKE /CS /RAS /CAS /WE BA0 H BA1 A10 Add Mode register set command Fig.2 Mode register set command (/CS, /RAS, /CAS, /WE Low) The EDD12xxALTA has a mode register that defines how the device operates. In this command, A0 through A11, BA0 and BA1 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During tMRD, the EDD12xxALTA can not accept any other commands. CLK CKE /CS /RAS /CAS /WE BA0,BA1 A10 Add H Bank activate command Fig.3 Bank activate command (/CS, /RAS = Low, /CAS, /WE = High) The EDD12xxALTA has four banks, each with 4,096 rows. This command activates the bank and the row address selected by BA0 and BA1, and by A0 through A11 respectively. This command corresponds to a conventional DRAM's /RAS falling. CLK CKE /CS /RAS /CAS /WE BA0,BA1 A10 Add H Row Row Preliminary Data Sheet E0136E30 11 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet EDD1204ALTA.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
EDD1204ALTA	128 M-bit Synchronous DRAM	Elpida Memory

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar