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EM488M3244VBC Schematic ( PDF Datasheet ) - Eorex

Teilenummer EM488M3244VBC
Beschreibung 256Mb Synchronous DRAM
Hersteller Eorex
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Gesamt 19 Seiten
EM488M3244VBC Datasheet, Funktion
eorex
Preliminary
EM488M3244VBC
256Mb (2M×4Bank×32) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 2.7V ~ 3.6V Power Supply
• LVCMOS Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• Deep Power Down Mode.
• Auto Refresh and Self Refresh
• Special Function Support.
– PASR (Partial Array Self Refresh)
– Auto TCSR (Temperature Compensated Self
Refresh)
• Programmable Driver Strength Control
– Full Strength or 1/2, 1/4 of Full Strength
• 4,096 Refresh Cycles / 64ms (15.625us)
Description
The EM488M3244VBC is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 32 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVCMOS.
Available packages: BGA-90B (13mmx8mm).
Ordering Information
Part No
EM488M3244VBC-75F
EM488M3244VBC-75FE
Organization
8M X 32
8M X 32
Max. Freq
133MHz @CL3
133MHz @CL3
Package
BGA-90B
BGA-90B
Grade Pb
Commercial Free
Extend temp. Free
* EOREX reserves the right to change products or specification without notice.
May. 2007
www.eorex.com
1/19






EM488M3244VBC Datasheet, Funktion
eorex
Block Diagram
Preliminary
EM488M3244VBC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
Auto/Self
Refresh Counter
DQM
Memory
Array
S/A & I/O Gating
Col. Decoder
Write DQM
Control
Data In
Data Out
Col. Add. Buffer
Mode Register Set
Col. Add. Counter
Burst Counter
Read DQM
Control
Timing Register
CLK CKE /CS /RAS /CAS /WE DQM
DOi
May. 2007
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6 Page









EM488M3244VBC pdf, datenblatt
eorex
Preliminary
EM488M3244VBC
Extended Mode Register Set ( EMRS )
The Extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA1 ( The
SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. )
The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is
written in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
10
0
0000
DS
00
PASR
Self Refresh Coverage
A2 A1 A0
All Banks
000
Two Banks (BA1=0)
001
One Bank (BA0=BA1=0)
010
Reserved
011
Reserved
100
Half of One Bank (BA0=BA1=0 ,Row Address MSB=0)
101
Quarter of One Bank (BA0=BA1=0 ,Row Address 2 MSB=0) 1 1 0
Reserved
111
Driver Strength
full
1/2 Strength
1/4 Strength
Reserved
A6
0
0
1
1
A5
0
1
0
1
BA1 MRS
0 Normal
1 EMRS
May. 2007
12/19
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