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PDF EM488M3244VBB Data sheet ( Hoja de datos )
| Número de pieza | EM488M3244VBB | |
| Descripción | 256Mb Synchronous DRAM | |
| Fabricantes | Eorex | |
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eorex
EM488M3244VBB
256Mb (2M×4Bank×32) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 3.3V ±0.3V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.625us)
Description
The EM488M3244VBB is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 32 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 256Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages: TFBGA-90B(13mmx8mm).
Ordering Information
Part No
EM488M3244VBB-75F
EM488M3244VBB-7F
EM488M3244VBB-75FE
EM488M3244VBB-7FE
Organization
8M X 32
8M X 32
8M X 32
8M X 32
Max. Freq
133MHz @CL3
143MHz @CL3
133MHz @CL3
143MHz @CL3
Package
TFBGA-90B
TFBGA-90B
TFBGA-90B
TFBGA-90B
Grade Pb
Commercial Free
Commercial Free
Extend temp. Free
Extend temp. Free
Jul. 2006
* EOREX reserves the right to change products or specification without notice.
1/18
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1 page  
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EM488M3244VBB
Absolute Maximum Rating
Symbol
Item
Rating
Units
VIN, VOUT
Input, Output Voltage
-0.3 ~ +4.6
V
VDD, VDDQ
Power Supply Voltage
-0.3 ~ +4.6
V
TOP Operating Temperature Range
Commercial 0 ~ +70
Extended -25 ~ +85
°C
TSTG
Storage Temperature Range
-55 ~ +150
°C
PD Power Dissipation
1W
IOS Short Circuit Current
50 mA
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could
cause permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Capacitance (VCC=3.3V, f=1MHz, TA=25°C)
Symbol
Parameter
Min. Typ. Max. Units
CCLK
CI
CO
Clock Capacitance
Input Capacitance for CLK, CKE, Address,
/CS, /RAS, /CAS, /WE, DQML, DQMU
Input/Output Capacitance
2.5
2.5
4.0
4.0 pF
3.0 pF
6.5 pF
Recommended DC Operating Conditions (TA=0°C ~70°C)
Symbol
Parameter
VDD Power Supply Voltage
VDDQ
Power Supply Voltage (for I/O Buffer)
VIH Input Logic High Voltage
VIL Input Logic Low Voltage
Note: * All voltages referred to VSS.
* VIH (max.) = 5.6V for pulse width 3ns
* VIL (min.) = -2.0V for pulse width 3ns
Min. Typ. Max. Units
3.0 3.3 3.6 V
3.0 3.3 3.6 V
2.0
VDD+0.3
V
-0.3 0.8 V
Jul. 2006
5/18
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EM488M3244VBB
Address Input for Mode Register Set
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Operation Mode
CAS Latency
BT Burst Length
Burst Length
Sequential Interleave A2 A1 A0
1 1 000
2 2 001
4 4 010
8 8 011
Reserved Reserved 1 0 0
Reserved Reserved 1 0 1
Reserved Reserved 1 1 0
Full Page Reserved 1 1 1
Burst Type
Interleave
Sequential
A3
1
0
CAS Latency
A6
A5
A4
Reserved
0
0
0
Reserved
0
0
1
2 010
3 011
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
BA1 BA0 A11 A10 A9 A8 A7
0000000
0000100
Operation Mode
Normal
Burst Read with Single-bit Write
Jul. 2006
11/18
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| PDF Descargar | [ Datasheet EM488M3244VBB.PDF ] | |
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