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EM47FM0888SBA Schematic ( PDF Datasheet ) - Eorex

Teilenummer EM47FM0888SBA
Beschreibung 4Gb Double DATA RATE 3 SDRAM
Hersteller Eorex
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Gesamt 30 Seiten
EM47FM0888SBA Datasheet, Funktion
EM47FM0888SBA
4Gb (64M× 8Bank×8) Double DATA RATE 3 low voltage SDRAM
Features
JEDEC Standard VDD/VDDQ = 1.5V±0.075V
All inputs and outputs are compatible with SSTL_15
interface.
Fully differential clock inputs (CK, /CK) operation.
Eight Banks
Posted CAS by programmable additive latency
Bust length: 4 with Burst Chop (BC) and 8.
CAS Write Latency (CWL): 5, 6, 7, 8
CAS Latency (CL): 6, 7, 8, 9, 10, 11
Write Latency (WL) =Read Latency (RL) -1.
Bi-directional Differential Data Strobe (DQS).
Data inputs on DQS centers when write.
Data outputs on DQS, /DQS edges when read.
On chip DLL align DQ, DQS and /DQS transition
with CK transition.
DM mask write data-in at the both rising and falling
edges of the data strobe.
Sequential & Interleaved Burst type available both
for 8 & 4 with BC.
Multi Purpose Register (MPR) for pre-defined
pattern read out
On Die Termination (ODT) options: Synchronous
ODT, Dynamic ODT, and Asynchronous ODT
Auto Refresh and Self Refresh
Refresh Interval: 7.8us Tcase between 0°C ~ 85°C
Refresh Interval: 3.9us Tcase between 85°C ~ 95°C
Refresh Interval: 7.8us Tcase between 0°C ~ 85°C
RoHS Compliance
Driver Strength: RZQ/7, RZQ/6(RZQ=240Ω)
High Temperature Self-Refresh rate enable
ZQ calibration for DQ drive and ODT
RESET pin for initialization and reset function
Description
The EM47FM0888SBA is a high speed Double Date
Rate 3 (DDR3) low voltage Synchronous DRAM
fabricated with ultra high performance CMOS
process containing 4,294,967,296 bits which
organized as 64Mbits x 8 banks by 8 bits. This
synchronous device achieves high speed
double-data-rate transfer rates of up to 1600
Mb/sec/pin (DDR3-1600) for general applications.
The chip is designed to comply with the following key
DDR3 SDRAM features: (1) posted CAS with
additive latency, (2) write latency = read latency -1,
(3) On Die Termination, (4) programmable driver
strength data,(5) seamless BL4 access with
bank-grouping. All of the control and address inputs
are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional
differential data strobes (DQS and /DQS) in a source
synchronous fashion. The address bus is used to
convey row, column and bank address information in
a /RAS and /CAS multiplexing style. The 4Gb DDR3
devices operates with a single power supply:
1.5V±0.075V VDD and VDDQ. Available
package: FBGA-78Ball (with 0.8mm x 0.8mm ball
pitch)
Jul. 2012
1/39
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EM47FM0888SBA Datasheet, Funktion
EM47FM0888SBA
Absolute Maximum Rating
Symbol
Item
Rating
Units
VIN, VOUT
VDD
VDDQ
Input, Output Voltage
Power Supply Voltage
Power Supply Voltage
-0.4 ~ +1.975
-0.4 ~ +1.975
-0.4 ~ +1.975
V
V
V
TOP
Operating Temperature Range
Commercial 0 ~ +95
°C
Extended
-25 ~ +95
TSTG
Storage Temperature Range
-55 ~ +100
°C
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings
could cause permanent damage. The device is not meant to be operated under conditions
outside the limits described in the operational section of this specification.
Recommended DC Operating Conditions
Symbol Parameter
Min.
Typ.
Max.
Units
VDD
VDDQ
Power Supply Voltage
Power Supply for I/O Voltage
1.425
1.425
1.5
1.575
V
1.5
1.575
V
Single-Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
Min. Max.
VIHCA (DC100)
VILCA (DC100)
DC input logic high
DC input logic low
VREF+0.100
VSS
VDD
VREF-0.100
VIHCA (AC175)
VILCA (AC175)
VIHCA (AC150)
AC input logic high
AC input logic low
AC input logic high
VREF+0.175
-
VREF+0.150
-
VREF-0.175
-
VILCA (AC150)
AC input logic low
- VREF-0.150
VREFCA (DC)
Reference voltage for ADD, CMD
0.49*VDD
0.51*VDD
Units
V
V
V
V
V
V
V
Single-Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
Min.
Max.
Units
VIHDQ (DC100)
VILDQ (DC100)
DC input logic high
DC input logic low
VREF+0.100
VSS
VDD
VREF-0.100
V
V
VIHDQ (AC175)
AC input logic high
- -V
VILDQ (AC175)
AC input logic low
- -V
VIHDQ (AC150)
AC input logic high
VREF+0.150 - V
VILDQ (AC150)
AC input logic low
- VREF-0.150 V
VREFDQ (DC)
Reference voltage for DQ, DM
0.49*VDD
0.51*VDD
V
Note1. For input pins except /RESET: VREF= VREFCA (DC) or VREF= VREFDQ (DC).
Note2. The AC peak noise on VREF may not allow VREF to deviate from VREFCA (DC) or VREF= VREFDQ (DC)
by more than ±1% VDD (for reference: approx. ±15mV.
Note3. For reference voltage = VDD/2 ±15mV.
Jul. 2012
6/39
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6 Page









EM47FM0888SBA pdf, datenblatt
EM47FM0888SBA
Recommended DC Operating Conditions
VDD/VDDQ = 1.5V±0.075V
Symbol Parameter & Test Conditions
IDD1
IDD2P1
IDD2N
IDD3P
IDD4W
IDD4R
IDD5B
Operating One Bank Active-Read-Precharge Current:
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see
timing used table; BL: 81; AL: 0; /CS: High between ACT, RD and
PRE; Command, Address, Data IO: partially toggling; DM:stable at 0;
Bank Activity: Cycling with one bank active at a time; Output Buffer
and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Precharge Power-Down Current Fast Exit:
CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: stable at 1; Command, Address: stable at 0; Data IO:
FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0;
Pre-charge Power Down Mode: Fast Exit
Precharge Standby Current:
CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: stable at 1; Command, Address: partially toggling; Data
IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers; ODT Signal:
stable at 0
Active Power-Down Current:
CKE: Low; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: stable at 1; Command, Address: stable at 0; Data IO:
FLOATING; DM: stable at 0; Bank Activity: all banks open; Output
Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Operating Burst Write Current:
CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: High between WR; Command, Address: partially toggling;
Data IO: seamless write data burst with different data between one
burst and the next one; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer
and RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH
Operating Burst Read Current:
CKE: High; External clock: On; tCK, CL: see timing used table; BL: 8;
AL: 0; /CS: High between RD; Command, Address: par-tially toggling;
Data IO: seamless read data burst with different data between one
burst and the next one; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer
and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Burst Refresh Current:
CKE: High; External clock: On; tCK, CL, nRFC: see timing used
table; BL: 8; AL: 0; /CS: High between REF; Command, Address:
partially toggling; Data IO: FLOATING; DM: stable at 0; Bank Activity:
REF command every nRFC; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0
-125 -150
Max
87 82
37 32
50 45
63 58
165 145
187 164
220 210
Units
mA
mA
mA
mA
mA
mA
mA
Jul. 2012
12/39
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