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PDF CD4093BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4093BMS | |
| Descripción | CMOS Quad 2-Input NAND Schmitt Triggers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4093BMS
December 1992
CMOS Quad 2-Input
NAND Schmitt Triggers
Features
Pinout
• High Voltage Types (20V Rating)
• Schmitt Trigger Action on Each Input With No External
Components
• Hysteresis Voltage Typically 0.9V at VDD = 5V and
2.3V at VDD = 10V
• Noise Immunity Greater than 50%
• No Limit on Input Rise and Fall Times
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range, 100nA at 18V and +25oC
CD4093BMSMS
TOP VIEW
A1
B2
J=A·B 3
K=C·D 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = G · H
10 L = E · F
9F
8E
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of Functional Diagram
‘B’ Series CMOS Devices”
Applications
• Wave and Pulse Shapers
• High Noise Environment Systems
• Monostable Multivibrators
• Astable Multivibrators
• NAND Logic
Description
CD4093BMS consists of four Schmitt trigger circuits. Each
circuit functions as a two input NAND gate with Schmitt trig-
ger action on both inputs. The gate switches at different
points for positive and negative going signals. The difference
between the positive voltage (VP) and the negative voltage
(VN) is defined as hysteresis voltage (VH) (see Figure 1).
The CD4093BMS is supplied in these 14 lead outline pack-
ages:
Braze Seal DIP H4H
Frit Seal DIP
H1B
Ceramic Flatpack H3W
A1
B2
J3
K4
C5
D6
VSS 7
J=A·B
14 VDD
13 H
K=C·D
L=E·F
12 G
11 M
10 L
9F
M=G·H
8E
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1074
File Number 3330
1 page  
Specifications CD4093BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 0.2µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION
Static Burn-In 1
Note 1
OPEN
3, 4, 10, 11
GROUND
1, 2, 5-9, 12, 13
VDD
14
9V ± -0.5V
OSCILLATOR
50kHz
25kHz
Static Burn-In 2 3, 4, 10, 11 7 1, 2, 5, 6, 8,
Note 1
9, 12-14
Dynamic Burn-
In Note 1
-
7
14
3, 4, 10, 11
1, 2, 5, 6,
-
8, 9, 12, 13
Irradiation
3, 4, 10, 11
7
1, 2, 5, 6, 8,
Note 2
9, 12-14
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Logic Diagram
VDD
1 (5, 8, 12) *
2 (6, 9, 13) *
* All inputs protected by CMOS protection network
3 (4, 10, 11)
1 OF 4 SCHMITT TRIGGERS
VSS
7-1078
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CD4093BMS.PDF ] | |
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