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Teilenummer | CD4077BMS |
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Beschreibung | CMOS Quad Exclusive OR and Exclusive NOR Gates | |
Hersteller | Intersil Corporation | |
Logo | ||
Gesamt 8 Seiten December 1992
CD4070BMS
CD4077BMS
CMOS Quad Exclusive OR and
Exclusive NOR Gates
Features
• High Voltage Types (20V Rating)
• CD4070BMS - Quad Exclusive OR Gate
• CD4077BMS - Quad Exclusive NOR Gate
• Medium Speed Operation
- tPHL, tPLH = 65ns (Typ.) at VDD = 10V, CL = 50pF
• 5V, 10V and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Pinouts
CD4070BMS
TOP VIEW
A1
B2
J = A⊕B 3
K = C⊕D 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = G⊕H
10 L = E⊕F
9F
8E
CD4077BMS
TOP VIEW
A1
B2
J = A⊕B 3
K = C⊕D 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = G⊕H
10 L = E⊕F
9F
8E
Applications
• Logical Comparators
• Parity Generators and Checkers
• Adders/Subtractors
Description
CD4070BMS contains four independent Exclusive OR gates.
The CD4077BMS contains four independent Exclusive NOR
gates.
The CD4070BMS and CD4077BMS provide the system
designer with a means for direct implementation of the
Exclusive OR and Exclusive NOR functions, respectively.
The CD4070BMS and CD4077BMS are supplied in these 14
lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4070B Only
H4Q
H1B
*H4F
†H3W
†CD4077B Only
Functional Diagram
J = A⊕B
K = C⊕D
M = G⊕H
L = E⊕F
VSS = 7
VDD = 14
1
A
2
B
5
C
6
D
8
E
9
F
G 12
13
H
CD4070BMS
J = A⊕B
K = C⊕D
M = G⊕H
L = E⊕F
1
A
2
B
5
C
6
D
8
E
9
F
G 12
13
H
3
J
4
K
10
L
11
M
3
J
4
K
10
L
11 M
CD4077BMS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-455
File Number 3322
Schematics
VDD
CD4070BMS, CD4077BMS
B*
2 (5, 9, 12)
p
n
n
VSS
VDD
p
VDD
p
p
A*
1 (6, 8, 13)
p
n
n
VDD
VSS
VSS
p
J
3 (4, 10, 11)
n
TRUTH TABLE CD4070BMS
1 OF 4 GATES
AB J
000
101
011
110
1 = High Level
0 = Low Level
J = A⊕B
* ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070BMS (1 OF 4 IDENTICAL GATES)
VDD
VDD
B*
2 (5, 9, 12)
p
n
n
p
p
n
VSS
VDD
A*
1 (6, 8, 13)
p
n
n
VDD
VSS
VSS
p
J
3 (4, 10, 11)
n
TRUTH TABLE CD4077BMS
1 OF 4 GATES
AB J
001
100
010
111
1 = High Level
0 = Low Level
J = A⊕B
* ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077BMS (1 OF 4 IDENTICAL GATES)
7-460
6 Page | ||
Seiten | Gesamt 8 Seiten | |
PDF Download | [ CD4077BMS Schematic.PDF ] |
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