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Teilenummer | P1350ETFS |
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Beschreibung | N-Channel Enhancement Mode Field Effect Transistor | |
Hersteller | NIKO-SEM | |
Logo | ||
Gesamt 4 Seiten NIKO-SEM
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PRODUCT SUMMARY
V(BR)DSS
RDS(ON)
500V
0.52Ω
ID
13A
D
G
S
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current2
Pulsed Drain Current1 , 2
Avalanche Current 3
Avalanche Energy3
TC = 25 °C
TC = 100 °C
VDS
VGS
ID
IDM
IAS
EAS
Power Dissipation
TC = 25 °C
TC = 100 °C
Operating Junction & Storage Temperature Range
PD
Tj, Tstg
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
Junction-to-Case
RJC
Junction-to-Ambient
RJA
1Pulse width limited by maximum junction temperature.
2Limited only by maximum temperature allowed
3VDD = 50V , L = 10mH ,starting ,TJ = 25˚C
TYPICAL
1. GATE
2. DRAIN
3. SOURCE
100% UIS tested
LIMITS
500
±30
13
8
45
4
80
39
15
-55 to 150
UNITS
V
V
A
mJ
W
°C
MAXIMUM
3.2
62.5
UNITS
°C / W
ELECTRICAL CHARACTERISTICS (TJ = 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC
MIN
LIMITS
TYP MAX
UNIT
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Gate Voltage Drain Current
V(BR)DSS
VGS(th)
IGSS
IDSS
VGS = 0V, ID = 250A
VDS = VGS, ID = 250A
VDS = 0V, VGS = ±30V
VDS = 500V, VGS = 0V , TC = 25 °C
VDS = 400V, VGS = 0V , TC = 100 °C
500
2
2.6 4
V
±100 nA
1
A
10
REV 1.0
1
F-34-3
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Seiten | Gesamt 4 Seiten | |
PDF Download | [ P1350ETFS Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
P1350ETF | N-Channel Enhancement Mode Field Effect Transistor | NIKO-SEM |
P1350ETFS | N-Channel Enhancement Mode Field Effect Transistor | NIKO-SEM |
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