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PDF CD4075BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4075BMS | |
| Descripción | CMOS OR Gate | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4071BMS, CD4072BMS
CD4075BMS
December 1992
CMOS OR Gate
Features
Pinout
• High-Voltage Types (20V Rating)
• CD4071BMS Quad 2-Input OR Gate
CD4071BMS
TOP VIEW
• CD4072BMS Dual 4-Input OR Gate
• CD4075BMS Triple 3-Input OR Gate
• Medium Speed Operation:
- tPHL, tPLH = 60ns (typ) at 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Standardized Symmetrical Output Characteristics
A1
B2
J=A+B 3
K=C+C 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = G + H
10 L = E + F
9F
8E
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4071BMS, CD4072BMS and CD4075BMS OR gates pro-
vide the system designer with direct implementation of the
positive-logic OR function and supplement the existing fam-
ily of CMOS gates.
CD4072BMS
TOP VIEW
J=A+B+C+D 1
A2
B3
C4
D5
NC 6
VSS 7
14 VDD
13 K = E +F + G + H
12 H
11 G
10 F
9E
8 NC
NC = NO CONNECTION
The CD4071BMS, CD4072BMS and CD4075BMS are supplied
in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4071, CD4072
*H4H †H4Q
H1B
H3W
†CD4075 Only
CD4075BMS
TOP VIEW
A1
B2
D3
E4
F5
K=D+E+F 6
VSS 7
14 VDD
13 G
12 H
11 I
10 L = G + H + I
9 J=A+B+C
8C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-444
File Number 3323
1 page  
Specifications CD4071BMS, CD4072BMS, CD4075BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Transition Time
Input Capacitance
SYMBOL
CONDITIONS
TTHL
TTLH
VDD = 10V
VDD = 15V
CIN Any Input
NOTES
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-
-
MAX
100
80
7.5
UNITS
ns
ns
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
∆VTN VDD = 10V, ISS = -10µA
VTP
∆VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
2.5
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - SSI
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
±0.1µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
7-448
5 Page | ||
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| PDF Descargar | [ Datasheet CD4075BMS.PDF ] | |
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