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PDF APW7325 Data sheet ( Hoja de datos )

Número de pieza APW7325
Descripción Synchronous Buck Converter
Fabricantes ANPEC 
Logotipo ANPEC Logotipo



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APW7325
5A 5V 1MHz Synchronous Buck Converter
Features
General Description
High Efficiency up to 95%
APW7325 is a 5A synchronous buck converter with inte-
- Automatic PFM/PWM Mode Operation
grated 65mhigh side and 55mlow side power
Adjustable Output Voltage from 0.6V to V
PVDD
MOSFETs. The APW7325, design with a current-mode
Integrated 65mHigh Side / 55mLow Side control scheme, can convert wide input voltage of 2.6V to
MOSFETs
Low Dropout Operation: 100% Duty Cycle
Stable with Low ESR Ceramic Capacitors
Power-On-Reset Detection on VDD and PVDD
6V to the output voltage adjustable from 0.6V to 6V to
provide excellent output voltage regulation.
The APW7325 is equipped with an automatic PFM/PWM
mode operation. At light load , the IC operates in the PFM
mode to reduce the switching losses. At heavy load, the
Integrated Soft-Start and Soft-Stop
IC works in PWM mode. At PWM mode, the switching
Over-Temperature Protection
frequency is set by the external resistor.
Over-Voltage Protection
The APW7325 is also equipped with Power-on-reset, soft-
Under-Voltage Protection
High/ Low Side Current Limit
Power Good Indication
Enable/Shutdown Function
Small SOP-8P Package
start, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature and current-limit) into a
single package.
This device, available SOP-8P, provides a very compact
system solution external components and PCB area.
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
Pin Configuration
Notebook Computer & UMPC
LCD Monitor/TV
Set-Top Box
DSL, Switch HUBr
Portable Instrument
NC 1
LX 2
NC 3
EN 4
APW7325
9
GND
8 GND
7 PVDD
6 VDD
5 FB
SOP-8P
(Top View)
9
GND
Exposed pad
The pin 6 must
be
connected
to
the
pin
9
(exposed
pad)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Sep., 2013
1
www.anpec.com.tw

1 page




APW7325 pdf
APW7325
Operating Waveforms
Refer to the typical application circuit. The test condition is V =5V, T = 25oC unless otherwise specified.
IN A
Load Transient Response
2.5A
1A
1
2
IOUT , 1A/Div
VOUT , 100mV/Div, AC
TIME: 20µs/Div
Normal Operating Waveform
VLX , 5V/Div
1
VOUT , 20mV/Div, DC
2
IL , 1A/Div
3
TIME: 1µs/Div
Load Transient Response
1.5A
10mA
1
IOUT , 1A/Div
2
VOUT , 100mV/Div, AC
TIME: 50µs/Div
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Sep., 2013
5
www.anpec.com.tw

5 Page





APW7325 arduino
APW7325
Application Information (Cont.)
Output Capacitor Selection (Cont.)
IL
IPEAK
IOUT
ILIM
IL
IP-FET
Layout Consideration
For all switching power supplies, the layout is an impor-
tant step in the design; especially at high peak currents
and switching frequencies. If the layout is not carefully
done, the regulator might show noise problems and duty
cycle jitter.
1. The input capacitor should be placed close to the PVDD
and GND. Connecting the capacitor and PVDD/GND
with short and wide trace without any via holes for good
input voltage filtering. The distance between VIN/GND
to capacitor less than 2mm respectively is
recommended.
2. To minimize copper trace connections that can inject
noise into the system, the inductor should be placed
as close as possible to the LX pin to minimize the
noise coupling into other circuits.
3. The output capacitor should be place closed to LX and
GND.
4. Since the feedback pin and network is a high imped-
ance circuit the feedback network should be routed
away from the inductor. The feedback pin and feed-
back network should be shielded with a ground plane
or trace to minimize noise coupling into this circuit.
5. A star ground connection or ground plane minimizes
ground shifts and noise is recommended.
Copyright © ANPEC Electronics Corp.
Rev. A.2 - Sep., 2013
11
www.anpec.com.tw

11 Page







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