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AD5700-1 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5700-1
Beschreibung Low Power HART Modem
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD5700-1 Datasheet, Funktion
Data Sheet
Low Power HART Modem
AD5700/AD5700-1
FEATURES
GENERAL DESCRIPTION
HART-compliant fully integrated FSK modem
1200 Hz and 2200 Hz sinusoidal shift frequencies
115 µA maximum supply current in receive mode
Suitable for intrinsically safe applications
Integrated receive band-pass filter
Minimal external components required
Clocking optimized for various system configurations
Ultralow power crystal oscillator (60 µA maximum)
External CMOS clock source
Precision internal oscillator (AD5700-1only)
Buffered HART output—extra drive capability
8 kV HBM ESD rating
1.71 V to 5.5 V power supply
1.71 V to 5.5 V interface
−40°C to +125°C operation
4 mm × 4 mm LFCSP package
HART physical layer compliant
UART interface
APPLICATIONS
Field transmitters
HART multiplexers
PLC and DCS analog I/O modules
HART network connectivity
The AD5700/AD5700-1 are single-chip solutions, designed
and specified to operate as a HART® FSK half-duplex modem,
complying with the HART physical layer requirements. The
AD5700/AD5700-1 integrateall of the necessary filtering, signal
detection, modulating, demodulating and signal generation
functions, thus requiring few external components. The 0.5%
precision internal oscillator on the AD5700-1 greatly reduces
the board space requirements, making it ideal for line-powered
applications in both master and slave configurations. The maxi-
mum supply current consumption is 115 µA, making the AD5700/
AD5700-1 an optimal choicefor lowpower loop-powered applica-
tions. Transmit waveforms are phase continuous 1200 Hz and
2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate
carrier detect circuitry and use a standard UART interface.
Table 1. Related Products
Part No. Description
AD5755-1 Quad-channel, 16-bit, serial input, 4 mA to20 mA and
voltage output DAC, dynamic power control, HART
connectivity
AD5421 16-bit, serial input, loop powered, 4 mA to 20 mA DAC
AD5410/ Single-channel, 12-bit/16-bit, serial input, 4 mA to 20 mA
AD5420 current source DACs
AD5412/ Single-channel, 12-bit/16-bit, serial input, current
AD5422 source and voltage output DACs
FUNCTIONAL BLOCK DIAGRAM
REG_CAP
CLKOUT XTAL1 XTAL2 XTAL_EN
VCC
IOVCC
DUPLEX
CD
RXD
TXD
RTS
OSC
FSK
MODULATOR
FSK
DEMODULATOR
AD5700/AD5700-1
DAC
BUFFER
ADC
BAND-PASS
FILTER AND
BIASING
HART_OUT
ADC_IP
HART_IN
CLK_CFG0
CLK_CFG1
VOLTAGE
REFERENCE
RESET
DGND
REF REF_EN
Figure 1.
AGND
FILTER_SEL
Rev. G
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AD5700-1 Datasheet, Funktion
AD5700/AD5700-1
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 4.
Parameter
VCC to GND
IOVCC to GND
Digital Inputs to DGND
Digital Output to DGND
HART_OUT to AGND
HART_IN to AGND
ADC_IP
AGND to DGND
Operating Temperature Range (TA)
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
Power Dissipation
Lead Temperature,
Soldering
ESD
Human Body Model
(ANSI/ESDA/JEDEC JS-001-
2010)
Field Induced Charge Model
(JEDEC JESD22_C101E)
Machine Model
(ANSI/ESD S5.2-2009)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to +2.5 V
−0.3 V to VCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to VCC + 0.3 V or
+7 V (whichever is less)
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
(TJ MAX – TA)/θJA
JEDEC industry standard
J-STD-020
8 kV
1.5 kV
400 V
Data Sheet
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
θJA1
24-Lead LFCSP
56
θJC
3
Unit
°C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with thermal vias. See JEDEC JESD51.
ESD CAUTION
Rev. G | Page 6 of 24

6 Page









AD5700-1 pdf, datenblatt
AD5700/AD5700-1
TERMINOLOGY
VCC and IOVCC Current Consumption
This specification gives a summation of the current consump-
tion of both the VCC and the IOVCC supplies. Figure 11 shows
separate measurements for VCC and IOVCC currents vs. varying
capacitive loads, in transmit mode.
Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/µA.
CD Assert
The minimum value at which the carrier detect signal asserts is
85 mV p-p and the maximumvalue it asserts at is 110 mV p-p. CD
is already high (asserted) for HART input signals greater than
110 mV p-p. This specification was set assuming a sinusoidal
input signal containing preamble characters at the input and an
ideal external filter (see Figure 23).
Data Sheet
HART_OUT Output Voltage
This is the peak-to-peak HART_OUT output voltage. The
specification in Table 2 was set using a worst-case load of 160 Ω,
ac-coupled with a 2.2 µF capacitor. Figure 17 and Figure 18 show
HART_OUT output voltages for both resistive and purely
capacitive loads.
Mark/Space Frequency
A 1.2 kHz signal represents a digital 1, or mark, whereas a
2.2 kHz signal represents a 0, or space.
Phase Continuity Error
The DDS engine in this design inherently generates continuous
phase signals, thus avoiding any output discontinuity when
switching between frequencies. This attribute is desirable for
signals that are to be transmitted over a band limited channel,
because discontinuities in a signal introduce wideband fre-
quency components. As the name suggests, for a signal to be
continuous, the phase continuity error must be 0o.
Rev. G | Page 12 of 24

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