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CD4053BC Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer CD4053BC
Beschreibung Single 8-Channel/ Dual 4-Channel/ Triple 2-Channel Analog Multiplexer/Demultiplexe
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 10 Seiten
CD4053BC Datasheet, Funktion
October 1989
CD4051BM CD4051BC Single 8-Channel Analog
Multiplexer Demultiplexer
CD4052BM CD4052BC Dual 4-Channel Analog
Multiplexer Demultiplexer
CD4053BM CD4053BC Triple 2-Channel Analog
Multiplexer Demultiplexer
General Description
These analog multiplexers demultiplexers are digitally con-
trolled analog switches having low ‘‘ON’’ impedance and
very low ‘‘OFF’’ leakage currents Control of analog signals
up to 15Vp-p can be achieved by digital signal amplitudes of
3 – 15V For example if VDDe5V VSSe0V and VEEeb5V
analog signals from b5V to a5V can be controlled by digi-
tal inputs of 0–5V The multiplexer circuits dissipate ex-
tremely low quiescent power over the full VDDbVSS and
VDDbVEE supply voltage ranges independent of the logic
state of the control signals When a logical ‘‘1’’ is present at
the inhibit input terminal all channels are ‘‘OFF’’
CD4051BM CD4051BC is a single 8-channel multiplexer
having three binary control inputs A B and C and an inhibit
input The three binary signals select 1 of 8 channels to be
turned ‘‘ON’’ and connect the input to the output
CD4052BM CD4052BC is a differential 4-channel multiplex-
er having two binary control inputs A and B and an inhibit
input The two binary input signals select 1 or 4 pairs of
channels to be turned on and connect the differential ana-
log inputs to the differential outputs
CD4053BM CD4053BC is a triple 2-channel multiplexer
having three separate digital control inputs A B and C and
an inhibit input Each control input selects one of a pair of
channels which are connected in a single-pole double-throw
configuration
Features
Y Wide range of digital and analog signal levels digital
3 – 15V analog to 15Vp-p
Y Low ‘‘ON’’ resistance 80X (typ ) over entire 15Vp-p sig-
nal-input range for VDDbVEEe15V
Y High ‘‘OFF’’ resistance channel leakage of g10 pA
(typ ) at VDDbVEEe10V
Y Logic level conversion for digital addressing signals of
3 – 15V (VDDbVSSe3 – 15V) to switch analog signals to
15 Vp-p (VDDbVEEe15V)
Y Matched switch characteristics DRONe5X (typ ) for
VDDbVEEe15V
Y Very low quiescent power dissipation under all digital-
control input and supply conditions 1 mW (typ ) at
VDDbVSSeVDDbVEEe10V
Y Binary address decoding on chip
Connection Diagrams
CD4051BM CD4051BC
Dual-In-Line Packages
CD4052BM CD4052BC
CD4053BM CD4053BC
Order Number CD4051B CD4052B or CD4053B
C1995 National Semiconductor Corporation TL F 5662
TL F 5662 – 1
RRD-B30M105 Printed in U S A






CD4053BC Datasheet, Funktion
Block Diagrams (Continued)
CD4053BM CD4053BC
Truth Table
INPUT STATES
‘‘ON’’ CHANNELS
INHIBIT C B A CD4051B CD4052B CD4053B
0 000
0
0X 0Y cx bx ax
0 001
1
1X 1Y cx bx ay
0 010
2
2X 2Y cx by ax
0 011
3
3X 3Y cx by ay
0 100
4
cy bx ax
0 101
5
cy bx ay
0 110
6
cy by ax
0 111
7
cy by ay
1
NONE
NONE
NONE
Don’t Care condition
TL F 5662 – 3
6

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