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PDF CD4051BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4051BMS | |
| Descripción | CMOS Analog Multiplexers/Demultiplexers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4051BMS, CD4052BMS
CD4053BMS
December 1992
CMOS Analog
Multiplexers/Demultiplexers*
Features
Description
• Logic Level Conversion
• High-Voltage Types (20V Rating)
• CD4051BMS Signal 8-Channel
• CD4052BMS Differential 4-Channel
• CD4053BMS Triple 2-Channel
• Wide Range of Digital and Analog Signal Levels:
- Digital 3V to 20V
- Analog to 20Vp-p
• Low ON Resistance: 125Ω (typ) Over 15Vp-p Signal
Input Range for VDD - VEE = 15V
• High OFF Resistance: Channel Leakage of ±100pA
(typ) at VDD - VEE = 18V
• Logic Level Conversion:
- Digital Addressing Signals of 3V to 20V (VDD - VSS
= 3V to 20V)
- Switch Analog Signals to 20Vp-p (VDD - VEE = 20V);
See Introductory Text
• Matched Switch Characteristics: RON = 5Ω (typ) for
VDD - VEE = 15V
• Very Low Quiescent Power Dissipation Under All Digi-
tal Control Input and Supply Conditions: 0.2µW (typ)
at VDD - VSS = VDD - VEE = 10V
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Break-Before-Making Switching Eliminates Channel
Overlap
Applications
CD4051BMS, CD4052BMS and CD4053BMS analog multi-
plexers/demultiplexers are digitally controlled analog
switches having low ON impedance and very low OFF leak-
age current. Control of analog signals up to 20V peak-to-
peak can be achieved by digital signal amplitudes of 4.5V to
20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be con-
trolled; for VDD-VEE level differences above 13V, a VDD-
VSS of at least 4.5V is required). For example, if VDD =
+4.5V, VSS = 0, and VEE = -13.5V, analog signals from -
13.5V to +4.5V can be controlled by digital inputs of 0 to 5V.
These multiplexer circuits dissipate extremely low quiescent
power over the full VDD-VSS and VDD-VEE supply voltage
ranges, independent of the logic state of the control signals.
When a logic “1” is present at the inhibit input terminal all
channels are off.
The CD4051BMS is a single 8 channel multiplexer having
three binary control inputs, A, B, and C, and an inhibit input.
The three binary signals select 1 of 8 channels to be turned
on, and connect one of the 8 inputs to the output.
The CD4052BMS is a differential 4 channel multiplexer hav-
ing two binary control inputs, A and B, and an inhibit input.
The two binary input signals select 1 of 4 pairs of channels
to be turned on and connect the analog inputs to the out-
puts.
The CD4053BMS is a triple 2 channel multiplexer having
three separate digital control inputs, A, B, and C, and an
inhibit input. Each control input selects one of a pair of chan-
nels which are connected in a single pole double-throw con-
figuration.
The CD4051BMS, CD4052BMS and CD4053BMS are supplied
in these 16 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4051B Only
*H4X
†H4T
H1E
H6W
†CD4052B, CD4053 Only
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
* When these devices are used as demultiplexers the “CHANNEL
IN/OUT” terminals are the outputs and the “COMMON OUT/IN” ter-
minals are the inputs.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-937
File Number 3316
1 page  
Specifications CD4051BMS, CD4052BMS, CD4053BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
(Note 1)
Address to Signal Out
Channels On or Off
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning On)
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning Off)
SYMBOL CONDITIONS (Notes 1, 2)
TPHL VDD = 5V, VIN = VDD or GND
TPLH VEE = VSS = 0V
GROUP A
SUBGROUPS TEMPERATURE
9 +25oC
10, 11
+125oC, -55oC
TPZH VDD = 5V, VIN = VDD or GND
TPZL VEE = VSS = 0V
9
10, 11
+25oC
+125oC, -55oC
TPHZ VDD = 5V, VIN = VDD or GND
TPLZ VEE = VSS = 0V
9
10, 11
+25oC
+125oC, -55oC
NOTES:
1. -55oC and +125oC limits guaranteed, 100% testing being implemented.
2. CL = 50pF, RL = 10KΩ, Input TR, TF < 20ns.
LIMITS
MIN MAX
- 720
- 972
- 720
- 972
- 450
- 608
UNITS
ns
ns
ns
ns
ns
ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
Input Voltage Low
Input Voltage High
Propagation Delay
Address to Signal Out
(Channels On or Off)
Propagation Delay
Inhibit to Signal Out
(Channel Turning On)
Propagation Delay
Inhibit to Signal Out
(Channel Turning Off)
Input Capacitance
SYMBOL
CONDITIONS
IDD VDD = 5V, VIN = VDD or GND
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
VIL VDD = VIS = 10V, VEE = VSS
RL = 1K to VSS
VIH |IIS|, 2µA On/Off Channel
TPHL
TPLH
TPZH
TPZL
TPHZ
TPLZ
CIN
VDD = 10V VEE = VSS = 0V
VDD = 15V
VDD = 5V
VEE = -5V
VDD = 10V VEE = VSS = 0V
VDD = 15V
VDD = 5V
VEE = -10V
VDD = 10V VEE = VSS = 0V
VDD = 15V
VDD = 5V
VEE = -15V
Any Address or Inhibit Input
NOTES
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
-55oC, +25oC
+125oC
-55oC, +25oC
+125oC
-55oC, +25oC
+125oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC
+25oC
+25oC
MIN
-
-
-
-
-
-
-
+7
-
-
-
+25oC
+25oC
+25oC
-
-
-
+25oC
+25oC
+25oC
-
-
-
+25oC
-
MAX
5
150
10
300
10
600
3
UNITS
µA
µA
µA
µA
µA
µA
V
-V
320 ns
240 ns
450 ns
320 ns
240 ns
400 ns
210 ns
160 ns
300 ns
7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are char-
acterized on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 10K, Input TR, TF < 20ns.
7-941
5 Page 
CD4051BMS, CD4052BMS, CD4053BMS
OUTPUT
RL 50pF
VEE
VDD
VSS
CLOCK
IN
VDD
VEE
VSS
1
2
3
4
5
6
7
8
tPHL AND tPLH
CD4051
VDD
16
15
14
13
12
11
10
9
VSS
OUTPUT
RL 50pF
VEE
VDD
VSS
CLOCK
IN
VDD
VEE
VSS
1
2
3
4
5
6
7
8
tPHL AND tPLH
CD4052
VDD
16
15
14
13
12
11
10
9
VSS
OUTPUT
RL 50pF
VEE
VDD
VSS
CLOCK
IN
VDD
VEE
VSS
1
2
3
4
5
6
7
8
tPHL AND tPLH
16 VDD
15
14
13
12
11
10
9
VSS
CD4053
FIGURE 13. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT
DIFFERENTIAL
SIGNALS
CD4052
CD4052
COMMUNICATIONS
LINK
DIFF
AMPLIFIER/
LINE DRIVER
DIFF
RECEIVER
DIFF
MULTIPLEXING
DEMULTIPLEXING
FIGURE 14. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052BMS
7-947
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet CD4051BMS.PDF ] | |
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