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84330CI Schematic ( PDF Datasheet ) - IDT

Teilenummer 84330CI
Beschreibung Crystal-to-LVPECL Frequency Synthesizer
Hersteller IDT
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Gesamt 20 Seiten
84330CI Datasheet, Funktion
720MHz, Low Jitter, Crystal-to-LVPECL
Frequency Synthesizer
84330CI
Data Sheet
General Description
The 84330CI is a general purpose, single output high frequency
synthesizer. The VCO operates at a frequency range of 250MHz to
720MHz. The VCO and output frequency can be programmed using
the serial or parallel interfaces to the configuration logic. The output
can be configured to divide the VCO frequency by 1, 2, 4, and 8.
Output frequency steps as small as 250kHz to 2MHz can be
achieved using a 16MHz crystal depending on the output divider
settings.
Features
Fully integrated PLL, no external loop filter requirements
One differential 3.3V LVPECL output
Crystal oscillator interface: 10MHz to 25MHz
Output frequency range: 31.25MHz to 720MHz
VCO range: 250MHz to 720MHz
Parallel or serial interface for programming M and N dividers
during power-up
RMS period jitter: 6ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Pin Assignments
Block Diagram
OE
XTAL1
XTAL2
FREF_EXT
Pullup
OSC
Pulldown
XTAL_SEL
Pullup
1
0
÷ 16
PLL
PHASE DETECTOR
VCO
÷M ÷2
÷2
1
÷4
÷8
÷1
0
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
Pulldown
Pulldown
Pulldown
Pullup
M0:M8
N0:N1
Pullup
Pullup
CONFIGURATION
INTERFACE
LOGIC
FOUT
nFOUT
TEST
25 24 23 22 21 20 19
S_CLOCK
S_DATA
S_LOAD
VCCA
FREF_EXT
XTAL_SEL
XTAL1
26 18
27 ICS84330CI 17
28 28 Lead PLCC 16
1
V Package
15
11.6mm x 11.4mm x 4.1mm
2
package body
14
3
Top View
13
4 12
5 6 7 8 9 10 11
N1
N0
M8
M7
M6
M5
M4
32 31 30 29 28 27 26 25
S_CLOCK 1
24 nc
S_DATA 2
S_LOAD 3
VCCA 4
VCCA 5
FREF_EXT 6
XTAL_SEL 7
ICS84330CI
32 Lead LQFP
Y Package
7mm x 7mm x 1.4mm
package body
Top View
23 N1
22 N0
21 M8
20 M7
19 M6
18 M5
XTAL1 8
17 M4
9 10 11 12 13 14 15 16
©2016 Integrated Device Technology, Inc
1
Revision A January 13, 2016






84330CI Datasheet, Funktion
84330CI Data Sheet
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum Typical Maximum
Fundamental
10 25
50
7
Units
MHz
pF
Table 6. Input Frequency Characteristics, VCC = 3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
XTAL; NOTE 1
10
fIN Input Frequency S_CLOCK
FREF_EXT; NOTE 2
10
Typical
Maximum
25
50
Units
MHz
MHz
MHz
NOTE 1: For the crystal frequency range, the M value must be set to achieve the minimum or maximum VCO frequency range of 250MHz to
720MHz. Using the minimum input frequency of 10MHz, valid values of M are 200 M 511. Using the maximum input frequency of 25MHz,
valid values of M are 80 M 230.
NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application Information Section for
recommendations on optimizing the performance using the FREF_EXT input.
AC Electrical Characteristics
Table 7. AC Characteristics, VCC = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
fOUT
tjit(per)
Output Frequency
Period Jitter, RMS; NOTE 1. 2
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2
fOUT 43.75MHz
fOUT < 43.75MHz
tR / tF
Output Rise/Fall Time
S_DATA to S_CLOCK
20% to 80%
tS Setup Time S_CLOCK to S_LOAD
M, N to nP_LOAD
S_DATA to S_CLOCK
tH
Hold Time
M, N to nP_LOAD
tL PLL Lock Time
odc Output Duty Cycle
Minimum
200
20
20
20
20
20
45
Typical
Maximum
720
6
40
50
600
10
55
Units
MHz
ps
ps
ps
ps
ns
ns
ns
ns
ns
ms
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
See Parameter Measurement Information section.
NOTE: Characterized using 16MHz XTAL.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: See Applications section.
©2016 Integrated Device Technology, Inc
6
Revision A January 13, 2016

6 Page









84330CI pdf, datenblatt
84330CI Data Sheet
The following component footprints are used in this layout example:
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors C3 and C4, as close as possible to
the power pins. If space allows, placement of the decoupling
capacitor on the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VCCA pin as possible.
Clock Traces and Termination
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the clock
signal is less tolerant to poor signal integrity than other signals. Any
ringing on the rising or falling edge or excessive ring back can cause
system failure. The shape of the trace and the trace delay might be
restricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
• The differential 50output traces should have the same
length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever possible,
avoid placing vias on the clock traces. Placement of vias on the
traces can affect the trace characteristic impedance and hence
degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace widths
between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Crystal
The crystal X1 should be located as close as possible to the pins 4
(XTAL1) and 5 (XTAL2). The trace length between the X1 and U1
should be kept to a minimum to avoid unwanted parasitic inductance
and capacitance. Other signal traces should not be routed near the
crystal traces.
C1
U1
X1
C2
PIN 2
PIN 1
C11 C16
VCCA
R7
GND
VCC
VCCA
VIA
Signals
Traces
C3
C4
50 Ohm
Traces
Figure 6B. 84330CI PCB Board Layout for 84330CI
©2016 Integrated Device Technology, Inc
12
Revision A January 13, 2016

12 Page





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