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813N252I-09 Schematic ( PDF Datasheet ) - IDT

Teilenummer 813N252I-09
Beschreibung VCXO Jitter Attenuator & FemtoClock Multiplier
Hersteller IDT
Logo IDT Logo 




Gesamt 23 Seiten
813N252I-09 Datasheet, Funktion
VCXO Jitter Attenuator &
FemtoClock® Multiplier
813N252I-09
Datasheet
General Description
The 813N252I-09 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation. The device contains two internal frequency
multiplication stages that are cascaded in series. The first stage is a
VCXO PLL that is optimized to provide reference clock jitter
attenuation. The second stage is a FemtoClock™frequency multiplier
that provides the low jitter, high frequency Ethernet output clock that
easily meets Gigabit and 10 Gigabit Ethernet jitter requirements.
Pre-divider and output divider multiplication ratios are selected using
device selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET and
Ethernet applications. The VCXO requires the use of an external,
inexpensive pullable crystal. The VCXO uses external passive loop
filter components which allows configuration of the PLL loop
bandwidth and damping characteristics. The device is packaged in a
space-saving 32-VFQFN package and supports industrial
temperature range.
Features
Two LVPECL output pairs
Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
Attenuates the phase jitter of the input clock by using a low-cost
pullable fundamental mode VCXO crystal
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking using external loop filter connection
FemtoClock frequency multiplier provides low jitter, high frequency
output
Absolute pull range: 50ppm
FemtoClock VCO frequency: 625MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.25ps (typical) and 0.35ps (maximum)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
32 31 30 29 28 27 26 25
LF1 1
24 VEE
LF0 2
23 nQB
ISET 3
22 QB
VEE 4
21 VCCO
CLK_SEL 5
20 nQA
VCC 6
19 QA
RESERVED 7
18 VEE
VEE 8
17 ODASEL_0
9 10 11 12 13 14 15 16
813N252I-09
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm EPad
K Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision C, December 10, 2015






813N252I-09 Datasheet, Funktion
813N252I-09 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, VCC
Inputs, VI
XTAL_IN
Other Inputs
Outputs, IO
Continuous Current
Surge Current
Package Thermal Impedance, JA
Storage Temperature, TSTG
Rating
3.63V
0V to VCC
-0.5V to VCC + 0.5V
50mA
100mA
37C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVPECL Power Supply DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCC
VCCA
VCCO
VCCX
IEE
ICCA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Charge Pump Supply Voltage
Power Supply Current
Analog Supply Current
3.135
VCC – 0.20
3.135
3.135
3.3
3.3
3.3
3.3
3.465
VCC
3.465
3.465
200
20
V
V
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = VCCX = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VIH Input High Voltage
VIL Input Low Voltage
CLK_SEL,
IIH
Input
High Current
ODASEL_[0:1],
ODBSEL_[0:1]
PDSEL_[0:2]
CLK_SEL,
IIL
Input
Low Current
ODASEL_[0:1],
ODBSEL_[0:1]
PDSEL_[0:2]
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465, VIN = 0V
2
-0.3
-10
-150
Maximum
VCC + 0.3
0.8
150
10
Units
V
V
µA
µA
µA
µA
©2015 Integrated Device Technology, Inc.
6
Revision C, December 10, 2015

6 Page









813N252I-09 pdf, datenblatt
813N252I-09 Datasheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1 R2
50Ω 50Ω
nCLK
Differential
Input
Figure 3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
*R3
HCSL
*R4
3.3V
CLK
nCLK
Differential
Input
Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
120Ω
R4
120Ω
3.3V
CLK
R1
120Ω
R2
120Ω
nCLK
Differential
Input
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver
©2015 Integrated Device Technology, Inc.
12
Revision C, December 10, 2015

12 Page





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