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P320HVN02.1 Schematic ( PDF Datasheet ) - AUO

Teilenummer P320HVN02.1
Beschreibung Color TFT-LCD
Hersteller AUO
Logo AUO Logo 




Gesamt 30 Seiten
P320HVN02.1 Datasheet, Funktion
P320HVN02.1 Product Specification
Rev. 0.0
Model Name: P320HVN02.1
Issue Date: 2015/03/05
()Preliminary Specifications
( )Final Specifications
Customer Signature
Date AUO
Date
Approved By
_________________________________
Approval By PM Director
Kelly Kao
____________________________________
Note
Reviewed By RD Director
Eugene CC Chen
____________________________________
Reviewed By Project Leader
Alex HM Chen
____________________________________
Prepared By PM
Bryan Chu
____________________________________
© Copyright AU Optronics Corp. 2014 All Rights Reserved.
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P320HVN02.1 Datasheet, Funktion
P320HVN02.1 Product Specification
Rev. 0.0
3. Electrical Specification
The P320HVN02.0 requires two power inputs. One is employed to power the LCD electronics and to drive the TFT
array and liquid crystal. The other is to power Back Light Unit.
3.1 Electrical Characteristics
3.1.1 DC Characteristics (Ta = 25 ± 2 °C)
Parameter
Symbol
LCD
Power Supply Input Voltage
Power Supply Input Current
Power Consumption
Inrush Current
Permissible Ripple of Power Supply Input Voltage
Input Differential Voltage
LVDS
Interface
Differential Input High Threshold
Voltage
Differential Input Low Threshold
Voltage
Input Common Mode Voltage
CMOS
Interface
Input High Threshold Voltage
Input Low Threshold Voltage
Backlight Power Consumption
Life time (MTTF)
VDD
IDD
PC
IRUSH
VRP
VID
VTH
VTL
VICM
VIH
(High)
VIL
(Low)
PBL
Min.
10.8
--
--
--
--
200
+100
-300
1.1
2.7
0
30000
Value
Typ.
Max
12
0.39
4.68
--
--
400
13.2
0.56
7.39
5
VDD * 5%
600
-- +300
-- -100
1.25 1.4
-- 3.3
-- 0.6
35.9 38.1
Unit
VDC
A
Watt
A
mVpk-pk
mVDC
mVDC
mVDC
VDC
VDC
VDC
Watt
Hour
Note
1
1
2
3
4
4
4
4
5
5
8, 9
3.1.2 AC Characteristics (Ta = 25 ± 2 °C)
Parameter
LVDS
Interface
Receiver Clock : Spread Spectrum
Modulation range
Receiver Clock : Spread Spectrum
Modulation frequency
Receiver Data Input Margin
Fclk = 85 MHz
Fclk = 65 MHz
Value
Symbol
Min. Typ.
Max
Fclk_ss
Fclk
-3%
--
Fclk
+3%
Fss 30 -- 200
Unit Note
MHz
6
KHz 6
tRMG
-0.4
--
0.4
ns 7
-0.5 --
0.5
© Copyright AU Optronics Corp. 2014 All Rights Reserved.
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P320HVN02.1 pdf, datenblatt
n LVDS Option = Low èJEIDA
P revious C ycle
C lo ck
P320HVN02.1 Product Specification
Rev. 0.0
C urrent C ycle
N ext Cycle
CHx_0+
CHx_0-
R3 R2 G2 R7 R6 R5 R4 R3 R2 G2
CHx_1+
CHx_1-
G4 G3 B3 B2 G7 G6 G5 G4 G3 B3
CHx_2+
CHx_2-
B5 B4 DE NA NA B7 B6 B5 B4 DE
CHx_3+
CHx_3-
R1 R0 NA B1 B0 G1 G0 R1 R0 NA
Note: x = 1, 2, 3, 4…
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