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PDF CD4042BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4042BMS | |
| Descripción | CMOS Quad Clocked D Latch | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4042BMS
December 1992
CMOS Quad Clocked “D” Latch
Features
Pinout
• High-Voltage Type (20V Rating)
• Clock Polarity Control
CD4042BMS
TOP VIEW
• Q and Q Outputs
• Common Clock
• Low Power TTL Compatible
Q4 1
Q1 2
Q1 3
16 VDD
15 Q4
14 D4
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• 5V, 10V and 15V Parametric Ratings
D1 4
CLOCK 5
POLARITY 6
D2 7
VSS 8
13 D3
12 Q3
11 Q3
10 Q2
9 Q2
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
NC = NO CONNECTION
Functional Diagram
D1 4
2 Q1
Applications
• Buffer Storage
• Holding Register
• General Digital Logic
Description
CD4042BMS types contain four latch circuits, each strobed by a
common clock. Complementary buffered outputs are available
from each circuit. The impedance of the n- and p- channel output
devices is balanced and all outputs are electrically identical.
D2 7
D3 13
D4 14
CLOCK
5
3 Q1
10 Q2
9 Q2
11 Q3
12 Q3
1 Q4
15 Q4
CL
Information present at the data input is transferred to outputs Q
and Q during the CLOCK level which is programmed by the
POLARITY input. For POLARITY = 0 the transfer occurs during
the 0 CLOCK level and for POLARITY = 1 the transfer occurs
during the 1 CLOCK level. The outputs follow the data input
defined above are present. When a CLOCK transition occurs
(positive for POLARITY = 0 and negative for POLARITY = 1) the
information present at the input during the CLOCK transition is
retained at the outputs until an opposite CLOCK transition
occurs.
POLARITY
6
VDD 16
VSS 8
The CD4042BMS is supplied in these 16 lead outline packages:
Braze Seal DIP H4T
Frit Seal DIP
H1E
Ceramic Flatpack H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-868
File Number 3310
1 page  
Specifications CD4042BMS
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 0.2µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE:
1. 1.5% parametric, 3% functional; cumulative for static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
TEST
METHOD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 1 - 3, 9 - 12, 15
Note 1
4 - 8, 13, 14
16
Static Burn-In 2 1 - 3, 9 - 12, 15 8 4 - 7, 13, 14, 16
Note 1
Dynamic Burn-
In Note 1
-
8
6, 16
1 - 3, 9 - 12, 15
5
4, 7, 13, 14
Irradiation
1 - 3, 9 - 12, 15
8
4 - 7, 13, 14, 16
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-872
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CD4042BMS.PDF ] | |
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