CD4041UBMS Datasheet PDF - Intersil Corporation
| Part Number | CD4041UBMS | |
| Description | CMOS Quad True/Complement Buffer | |
| Manufacturers | Intersil Corporation | |
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Data Sheet
CD4041UBMS
December 1992
File Number 3309
CMOS Quad True/Complement Buffer
CD4041UBMS types are quad true/complement buffers con-
sisting of n- and p- channel units having low channel resis-
tance and high current (sourcing and sinking) capability. The
CD4041UBMS is intended for use as a buffer, line driver, or
CMOS-to-TTL driver. It can be used as an ultra-low power
resistor-network driver for A/D and D/A conversion, as a
transmission-line driver, and in other applications where high
noise immunity and low power dissipation are primary
design requirements.
The CD4041UBMS is supplied in these 14 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
Pinout
CD4041UBMS
TOP VIEW
E=A 1
F=A 2
A3
G=B 4
H=B 5
B6
VSS 7
14 VDD
13 D
12 N = D
11 M = D
10 C
9 L=C
8 K=C
Features
• High Voltage Type (20V Rating)
• Balanced Sink and Source Current; Approximately 4
Times Standard “B” Drive
• Equalized Delay to True and Complement Outputs
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specificationsfor Description of
‘B’ Series CMOS Devices”
Applications
• High Current Source/Sink Driver
• CMOS-to-DTL/TTL Converter Buffer
• Display Driver
• MOS Clock Driver
• Resistor Network Driver (Ladder or Weighted R)
• Buffer
• Transmission Line Driver
Functional Diagram
3
A
6
B
10
C
13
D
VSS = 7
VDD = 14
1
E
E=A
2
F
F=A
4
G
G=B
5
H
H=B
8
K
K=C
9
L
L=C
11
M
M=D
12
N
N=D
VDD
VDD VDD
INPUT*
TRUE
OUTPUT
VSS
*ALL INPUTS PROTECTED
BY CMOS INPUT
PROTECTION NETWORK
VSS
VSS
P
N
VSS
VDD
COMPLEMENT
OUTPUT
VDD
VSS
FIGURE 1. SCHEMATIC DIAGRAM 1 OF 4 BUFFERS
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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CD4041UBMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
5005
TEST
PRE-IRRAD
POST-IRRAD
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9, Deltas
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 1, 2, 4, 5, 8, 9, 11,
(Note 1)
12
3, 6, 7, 10, 13
14
Static Burn-In 2 1, 2, 4, 5, 8, 9, 11,
(Note 1)
12
7
3, 6, 10, 13, 14
Dynamic Burn-
In (Note 2)
-
7
14
1, 2, 4, 5, 8, 9, 11,
3, 6, 10, 13
12
Irradiation
(Note 3)
1, 2, 4, 5, 8, 9, 11,
12
7
3, 6, 10, 13, 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 4.75K ± 5%; VDD = 18V ± 0.5V
3. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ±
0.5V
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
70
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
60
50
10V
40
30
20
5V
10
0 1 2 345 678
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
70
60
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
50
40
30 10V
20
10
5V
0 1 2 345 678
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. MINIMUM LOW (SINK) CURRENT CHARACTERIS-
TICS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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