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AD565A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD565A
Beschreibung High Speed 12-Bit Monolithic D/A Converters
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 13 Seiten
AD565A Datasheet, Funktion
a
High Speed 12-Bit
Monolithic D/A Converters
FEATURES
Single Chip Construction
Very High Speed Settling to 1/2 LSB
AD565A: 250 ns max
AD566A: 350 ns max
Full-Scale Switching Time: 30 ns
Guaranteed for Operation with ؎12 V (565A) Supplies,
with –12 V Supply (AD566A)
Linearity Guaranteed Overtemperature
1/2 LSB max (K, T Grades)
Monotonicity Guaranteed Overtemperature
Low Power: AD566A = 180 mW max;
AD565A = 225 mW max
Use with On-Board High Stability Reference (AD565A)
or with External Reference (AD566A)
Low Cost
MlL-STD-883-Compliant Versions Available
AD566A is obsolete
PRODUCT DESCRIPTION
The AD565A and AD566A are fast 12-bit digital-to-analog
converters that incorporate the latest advances in analog circuit
design to achieve high speeds at low cost.
The AD565A and AD566A use 12 precision, high speed bipolar
current-steering switches, a control amplifier, and a laser-trimmed
thin-film resistor network to produce a very fast, high accuracy
analog output current. The AD565A also includes a buried
Zener reference that features low noise, long-term stability, and
temperature drift characteristics comparable to the best discrete
reference diodes.
The combination of performance and flexibility in the AD565A and
AD566A has resulted from major innovations in circuit design,
an important new high speed bipolar process, and continuing
advances in laser-wafer-trimming techniques (LWT). The
AD565A and AD566A have a 10%–90% full-scale transition
time less than 35 ns and settle to within ±1/2 LSB in 250 ns max
(350 ns for AD566A). Both are laser-trimmed at the wafer level
to ± 1/8 LSB typical linearity and are specified to ± 1/4 LSB max
error (K and T grades) at +25°C. High speed and accuracy make
the AD565A and AD566A the ideal choice for high speed display
drivers as well as for fast analog-to-digital converters.
The laser trimming process that provides the excellent linearity
is also used to trim both the absolute value and the temperature
coefficient of the reference of the AD565A, resulting in a typical
full-scale gain TC of 10 ppm/°C. When tighter TC performance
is required or when a system reference is available, the AD566A
may be used with an external reference.
TheAD566Aisnolongeravailable.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
AD565A
FUNCTIONAL BLOCK DIAGRAMS
REF OUT
VCC
BIPOLAR OFF
REF
IN
REF
GND
10V
19.95k
20k
AD565A
0.5mA
9.95k
IREF
DAC
IOUT =
4 ؋ IREF ؋ CODE
5k
5k
IO 8k
20V SPAN
10V SPAN
DAC OUT
CODE INPUT
–VEE
REF
IN
19.95k
REF
GND
20k
POWER MSB
GND
LSB
BIPOLAR OFF
AD566A
0.5mA
9.95k
IREF
DAC
IOUT =
4 ؋ IREF ؋ CODE
5k
5k
IO 8k
20V SPAN
10V SPAN
DAC OUT
CODE INPUT
–VEE
POWER MSB
GND
LSB
AD565A and AD566A are available in four performance
grades. The J and K grades are specified for use over the 0°C to
+70°C temperature range while the S and T grades are speci-
fied for the –55°C to +125°C range. The D grades are all pack-
aged in a 24-lead, hermetically sealed, ceramic, dual-in-line
package. The JR grade is packaged in a 28-lead plastic SOIC.
PRODUCT HIGHLIGHTS
1. The wide output compliance range of the AD565A and
AD566A are ideally suited for fast, low noise, accurate voltage
output configurations without an output amplifier.
2. The devices incorporate a newly developed, fully differential,
nonsaturating precision current switching cell structure that
combines the dc accuracy and stability first developed in the
AD562/AD563 with very fast switching times and an optimally
damped settling characteristic.
3. The devices also contain SiCr thin-film application resistors
that can be used with an external op amp to provide a preci-
sion voltage output or as input resistors for a successive-
approximation A/D converter. The resistors are matched to
the internal ladder network to guarantee a low gain temperature
coefficient and are laser-trimmed for minimum full-scale and
bipolar offset errors.
4. The AD565A and AD566A are available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military
Products Databook or current /883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/461-3113
© Analog Devices, Inc., 2015






AD565A Datasheet, Funktion
AD565A
Parameter
AD566AS
Min Typ Max
AD566AT
Min Typ Max
Unit
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1”
Bit OFF Logic “0”
Logic Current (Each Bit)
Bit ON Logic “1”
Bit OFF Logic “0”
RESOLUTION
OUTPUT
Current
Unipolar (All Bits On)
Bipolar (All Bits On or Off)
Resistance (Exclusive of Span Resistors)
Offset
Unipolar (Adjustable to Zero per Figure 3)
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed)
Capacitance
Compliance Voltage
TMIN to TMAX
ACCURACY (Error Relative to
Full Scale) 25°C
TMIN to TMAX
DIFFERENTIAL NONLINEARITY
25°C
TMIN to TMAX
TEMPERATURE COEFFICIENTS
Unipolar Zero
Bipolar Zero
Gain (Full Scale)
Differential Nonlinearity
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time
90% to 10% Delay plus Fall Time
POWER REQUIREMENTS
VEE, –11.4 to –16.5 V dc
POWER SUPPLY GAIN SENSITIVITY2
VEE = –11.4 to –16.5 V dc
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5)
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3)
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4)
Gain Adjustment Range (Figure 3)
Bipolar Zero Adjustment Range
REFERENCE INPUT
Input Impedance
POWER DISSIPATION
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants
Reference Voltage
Accuracy
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to 10 V [p-p], Sine Wave
Frequency for l/2 LSB [p-p] Feedthrough)
Output Slew Rate 10%–90%
90%–10%
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage)
CONTROL AMPLIFIER
Full Power Bandwidth
Small-Signal Closed-Loop Bandwidth
2.0 5.5
0 0.8
120 300
35 100
12
2.0 5.5
0 0.8
+120
+35
300
100
12
–1.6
؎0.8
6
–1.5
–2.0
± 1.0
8
0.01
0.05
25
–2.4
؎1.2
10
0.05
0.15
+10
–1.6
؎0.8
6
–1.5
–2.0 –2.4
± 1.0 ؎1.2
8 10
0.01 0.05
0.05 0.1
25
+10
± 1/4
(0.006)
± 1/2
(0.012)
؎1/2
(0.012)
؎3/4
(0.018)
± 1/8
(0.003)
± 1/4
(0.006)
؎0.35
(0.0084)
؎1/2
(0.012)
± 1/2 ؎3/4
± 1/4 ؎1/2
MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
12
5 10
7 10
2
12
5 10
35
2
250 350
250 350
15 30
30 50
15 30
30 50
–12 –18
–12 –18
15 25
15 25
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
0 to +5
–2.5 to +2.5
0 to +10
–5 to +5
–10 to +10
± 0.25
± 0.15
15
± 0.1
± 0.05
؎0.25
؎0.15
± 0.25
± 0.15
± 0.1
± 0.05
؎0.25
؎0.1
20 25
15 20 25
180 300
180 300
Two (2): Bipolar Operation at Digital Input Only
1 V to 10 V, Unipolar
10 Bits (± 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
40
5
1
1.5 μs to 0.01% F.S.
300
1.8
V
V
μA
μA
Bits
mA
mA
kΩ
% of F.S. Range
% of F.S. Range
pF
V
LSB
% of F.S. Range
LSB
% of F.S. Range
LSB
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ns
ns
ns
mA
ppm of F.S./%
V
V
V
V
V
% of F.S. Range
% of F.S. Range
% of F.S. Range
% of F.S. Range
kΩ
mW
kHz typ
mA/μs
mA/μs
kHz
MHz
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specification subject to change without notice.
REV. F
–5–

6 Page









AD565A pdf, datenblatt
OUTLINE DIMENSIONS
0.005 (0.13) MIN
0.098 (2.49) MAX
24 13
0.610 (15.49)
0.500 (12.70)
PIN 1
1
2
1.290 (32.77) MAX
0.075 (1.91)
0.225 (5.72)
MAX
0.200 (5.08)
0.015 (0.38)
0.150
(3.81)
MIN
0.120 (3.05)
0.023 (0.58)
0.014 (0.36)
0.100 (2.54) 0.070 (1.78)
BSC 0.030 (0.76)
SEATING
PLANE
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 7. 24-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-24-2)
Dimensions shown in inches and (millimeters)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
18.10 (0.7126)
17.70 (0.6969)
28 15
7.60 (0.2992)
7.40 (0.2913)
1 14 10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.33 (0.0130)
0.20 (0.0079)
0.75 (0.0295)
0.25 (0.0098) 45°
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013-AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 8. 28-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
AD565A
Rev. F | Page 11

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