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PDF AD671 Data sheet ( Hoja de datos )
| Número de pieza | AD671 | |
| Descripción | Monolithic 12-Bit 2 MHz A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Monolithic 12-Bit
2 MHz A/D Converter
AD671
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-Bit Resolution
24-Pin “Skinny DIP” Package
Conversion Time: 500 ns max—AD671J/K/S-500
AIN BPO/UPO ENCODE REF IN VCC ACOM VEE VLOGIC
20 21
16 19 23 22 24 17
DCOM
18
Conversion Time: 750 ns max—AD671J/K/S-750
Low Power: 475 mW
RANGE
SELECT
X4
Unipolar (0 V to +5 V, 0 V to +10 V) and Bipolar Input
COARSE
8-BIT
Ranges (؎5 V)
Twos Complement or Offset Binary Output Data
Out-of-Range Indicator
MIL-STD-883 Compliant Versions Available
OBSPRODUCT DESCRIPTION
OThe AD671 is a high speed monolithic 12-bit A/D converter
offering conversion rates of up to 2 MHz (500 ns conversion
Ltime). The combination of a merged high speed bipolar/CMOS
Eprocess and a novel architecture results in a combination of
speed and power consumption far superior to previously avail-
TEable hybrid implementations. Additionally, the greater reliability
3-BIT
FLASH
DAC
3-BIT
FLASH
DAC
4-BIT
FLASH
LADDER
MATRIX
3
AD671
3
CORRECTION LOGIC
4
8
LATCHES
FINE
4-BIT
FLASH
4
12
14 13
OTR MSB
12 1
BIT1-12
15
DAV
PRODUCT HIGHLIGHTS
1. The AD671 offers a single chip 2 MHz analog-to-digital
conversion function in a space saving 24-pin DIP.
2. Input signal ranges are 0 V to +5 V and 0 V to +10 V unipo-
lar, and –5 V to +5 V bipolar, selected by pin strapping. In-
put resistance is 1.5 kΩ. Power supplies are +5 V and –5 V,
and typical power consumption is less than 500 mW.
of monolithic construction offers improved system reliability
and lower costs than hybrid designs.
3. The external +5 V reference can be chosen to suit the dc ac-
The AD671 uses a subranging flash conversion technique, with
curacy and temperature drift requirements of the application.
digital error correction for possible errors introduced in the first 4. Output data is available in unipolar, bipolar offset or bipolar
part of the conversion cycle. An on-chip timing generator pro-
twos complement binary format.
vides strobe pulses for each of the four internal flash cycles and
assures adequate settling time for the interflash residue ampli-
fier. A single ENCODE pulse is used to control the converter.
The performance of the AD671 is made possible by using high
speed, low noise bipolar circuitry in the linear sections and low
power CMOS for the logic sections. Analog Devices’ ABCMOS-1
process provides both high speed bipolar and 2-micron CMOS
5. An OUT OF RANGE output bit indicates when the input
signal is beyond the AD671’s input range.
6. The AD671 is available in versions compliant with the MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD671/883B data sheet for detailed
specifications.
devices on a single chip. Laser trimmed thin-film resistors are
used to provide accuracy and temperature stability.
The AD671 is available in two conversion speeds and perfor-
mance grades. The AD671J and K grades are specified for op-
eration over the 0°C to +70°C temperature range. The AD671S
grades are specified for operation over the –55°C to +125°C
temperature range. All grades are available in a 0.300 inch wide
24-pin ceramic DIP. The J and K grades are also available in a
24-pin plastic DIP.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD671
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
With
Temperature Package
Respect
Modell
Linearity Range
Options2
Parameter
to Min Max Units
AD671JD-500 ± 4 LSB
0°C to +70°C
D-24A
VCC
VEE
VLOGIC
ACOM
ACOM –0.5 +6.5
ACOM –6.5 +0.5
DCOM –0.5 +6.5
DCOM –1.0 +1.0
Volts
Volts
Volts
Volts
AD671KD-500
AD671JD-750
AD671KD-750
AD671SD-500
± 2 LSB
± 2 LSB
± 1.5 LSB
± 4 LSB
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
D-24A
D-24A
D-24A
D-24A
VCC
VLOGIC –6.5 +6.5
Volts AD671SD-750 ± 2.5 LSB –55°C to +125°C D-24A
ENCODE
REF IN
AIN, BPO/UPO
DCOM –0.5 VLOGIC +0.5 Volts
ACOM –0.5 VCC +0.5 Volts
ACOM –6.5 11.0
Volts
NOTES
1For details on grade and package offerings screened in accordance with
MIL-STD-883, refer to the Analog Devices Military Products Databook or
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
Power Dissipation
+175
–65 +150
+300
1000
°C
°C
°C
mW
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
Ooperation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
Bmaximum ratings for extended periods may effect device reliability.
current AD671/883 data sheet.
2D = Ceramic DIP.
SOCAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
L WARNING!accumulate on the human body and test equipment and can discharge without detection.
Although the AD671 features proprietary ESD protection circuitry, permanent damage may
Eoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
TEprecautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
REV. B
–5–
5 Page 
AD671
MSB
OTR
OVER = "1"
MSB
UNDER = "1"
Figure 11. Overrange or Underrange Logic
OUTPUT DATA FORMAT
The AD671 provides both MSB and MSB outputs, delivering
data in positive true straight binary for unipolar input ranges
and positive true offset binary or twos complement for bipolar
input ranges. Straight binary coding is used for systems that ac-
cept positive-only signals. If straight binary coding is used with
bipolar input signals a 0 V input would result in a binary output
of 2048. The application software would have to subtract 2048
to determine the true input voltage. Most processors typically
perform math on signed integers and assume data is in that for-
mat. Twos complement format minimizes software overhead
which is especially important in high speed data transfers, such
as a DMA operation. The CPU is not bogged down performing
data conversion steps, hence increasing the total system
throughput.
Input
Range
0 to +5 V
OBS0 to +10 V
OLETE–5Vto+5V
Table III. Output Data Format
Coding
Straight Binary
Straight Binary
Offset Binary
Analog
Input1
≤ –0.00061 V
0V
+5 V
>+5.00061 V
≤ –0.00122 V
0V
+10 V
≥ +10.00122 V
≤ –5.00122 V
–5 V
0V
Digital
Output
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
0000 0000 0000
0000 0000 0000
1000 0000 0000
OTR2
1
0
0
1
1
0
0
1
1
0
0
+4.99756 V
1111 1111 1111
0
≥ +4.99878 V 1111 1111 1111
1
–5 V to +5 V 2s Complement
(Using MSB)
≤ –5.00122 V
–5 V
0V
+4.99756 V
≥ +4.99878 V
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
1
0
0
0
1
NOTES
1Voltages listed are with offset and gain errors adjusted to zero.
2Typical performance.
ILOGIC vs. CONVERSION RATE
Figure 12 shows the typical logic supply current vs. conversion
rate for various capacitive loads on the digital outputs.
REV. B
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
1k
CL = 50pF
CL = 30pF
CL = 0pF
10k 100k
1M
CONVERSION RATE – Hz
10M
Figure 12. ILOGIC vs. Conversion Rate for Various
Capacitive Loads on the Digital Outputs
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD671.PDF ] | |
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