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AD6644 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD6644
Beschreibung 40 MSPS/65 MSPS Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD6644 Datasheet, Funktion
14-Bit, 40 MSPS/65 MSPS
Analog-to-Digital Converter
AD6644
FEATURES
65 MSPS guaranteed sample rate
40 MSPS version available
Sampling jitter < 300 fs
100 dB multitone SFDR
1.3 W power dissipation
Differential analog inputs
Pin compatible to AD6645
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
APPLICATIONS
Multichannel, multimode receivers
AMPS, IS-136, CDMA, GSM, WCDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radar, infrared imaging
Instrumentation
GENERAL DESCRIPTION
The AD6644 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (TH) and reference, are included on-
chip to provide a complete conversion solution. The AD6644
provides CMOS-compatible digital outputs. It is the third
generation in a wideband ADC family, preceded by the AD9042
(12-bit 41 MSPS) and the AD6640 (12-bit 65 MSPS, IF
sampling).
Designed for multichannel, multimode receivers, the AD6644
is part of the Analog Devices, Inc. new SoftCell® transceiver
chipset. The AD6644 achieves 100 dB multitone, spurious-free
dynamic range (SFDR) through the Nyquist band. This break-
through performance eases the burden placed on multimode
digital receivers (software radios) which are typically limited by
the ADC. Noise performance is exceptional; typical signal-to-
noise ratio is 74 dB.
The AD6644 is also useful in single channel digital receivers
designed for use in wide-channel bandwidth systems (CDMA,
WCDMA). With oversampling, harmonics can be placed
outside the analysis bandwidth. Oversampling also facilitates
the use of decimation receivers (such as the AD6620), allowing
the noise floor in the analysis bandwidth to be reduced. By
replacing traditional analog filters with predictable digital
components, modern receivers can be built using fewer RF
components, resulting in decreased manufacturing costs, higher
manufacturing yields, and improved reliability.
The AD6644 is built on the Analog Devices high speed
complementary bipolar process (XFCB) and uses an innovative,
multipass circuit architecture. Units are packaged in a 52-lead
plastic low profile quad flat package (LQFP) specified from –
25°C to +85°C.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage.
3. Digital outputs can be run on 3.3 V supply for easy interface
to digital ASICs.
4. Complete solution: reference and track-and-hold.
5. Packaged in small, surface-mount, plastic, 52-lead LQFP.
AVCC DVCC
FUNCTIONAL BLOCK DIAGRAM
AIN A1 TH1
AIN
VREF
2.4V
ENCODE
ENCODE
INTERNAL
TIMING
TH2
A2 TH3
TH4
TH5 ADC3
ADC1 DAC1
5
ADC2 DAC2
5
DIGITAL ERROR CORRECTION LOGIC
AD6644
6
GND
DMID OVR DRY D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
(LSB)
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.






AD6644 Datasheet, Funktion
AD6644
Parameter
DATA READY (DRY6)/DATA, OVR
Data Ready to DATA Delay (Hold Time)3
Encode = 65 MSPS (50% Duty Cycle)
Encode = 40 MSPS (50% Duty Cycle)
Data Ready to DATA Delay (Setup Time)3
@ 65 MSPS (50% Duty Cycle)
@ 40 MSPS (50% Duty Cycle)
APERTURE DELAY
APERTURE UNCERTAINTY (JITTER)
Name
tH_DR
tS_DR
tA
tJ
Temp Test Level1
Full IV
Full IV
Full IV
Full IV
25°C V
25°C V
AD6644AST-40/65
Min Typ Max
See note7
8.0 8.6 9.4
12.8 13.4 14.2
See note7
3.2 5.5 6.5
8.0 10.3 11.3
100
0.2
Unit
ns
ns
ns
ns
ps
ps rms
1 See the Explanation of Test Levels section.
2 Several timing parameters are a function of tENC and tENCH.
3 To compensate for a change in duty cycle for tH_DR and tS_DR use the following equations:
NewtH_DR = (tH_DR − % Change(tENCH)) × tENC/2
NewtS_DR = (tS_DR − % Change(tENCH)) × tENC/2
4 ENCODE to data delay (hold time) is the absolute minimum propagation delay through the ADC.
5 ENCODE to data delay (setup time) is calculated relative to 65 MSPS (50% duty cycle). To calculate tS_E for a given encode, use the following equation:
NewtS_E = tENC(NEW) tENC + tS_E (that is, for 40 MSPS, NewtS_E(TYP) = 25 × 10−9 − 15.38 × 10−9 + 9.8 × 10−9 = 19.4 × 10−9).
6 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock correspondingly changes the duty cycle of DRY.
7 Data ready to data delay (tH_DR and tS_DR) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on tENC and duty cycle. To calculate tH_DR and tS_DR for a
given encode, use the following equations:
NewtH_DR = tENC(NEW)/2 − tENCH + tH_DR (that is, for 40 MSPS, NewtH_DR(TYP) = 12.5 × 10−9 − 7.69 × 10−9 + 8.6 × 10−9 = 13.4 × 10−9).
NewtS_DR = tENC(NEW)/2 − tENCH + tS_DR (that is, for 40 MSPS, NewtS_DR(TYP) = 12.5 × 10−9 − 7.69 × 10−9 + 5.5 × 10−9 = 10.3 × 10−9).
AC SPECIFICATIONS
All ac specifications tested by driving ENCODE and ENCODE differentially.
AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = maximum conversion rate MSPS; TMIN = −25°C, TMAX = +85°C, unless otherwise noted.
Table 5.
Parameter
SNR
Analog Input
@ −1 dBFS
SINAD2
Analog Input
@ −1 dBFS
WORST HARMONIC (2ND or 3RD)2
Analog Input
@ −1 dBFS
WORST HARMONIC (4TH or Higher)2
Analog Input
@ −1 dBFS
TWO-TONE SFDR2, 3, 4
TWO-TONE IMD REJECTION2, 4
F1, F2 @ −7 dBFS
ANALOG INPUT BANDWIDTH
Conditions
2.2 MHz
15.5 MHz
30.5 MHz
2.2 MHz
15.5 MHz
30.5 MHz
2.2 MHz
15.5 MHz
30.5 MHz
2.2 MHz
15.5 MHz
30.5 MHz
Temp
Test Level1
AD6644AST-40
Min Typ Max
AD6644AST-65
Min Typ Max
Unit
25°C V
25°C II
25°C II
74.5 74.5 dB
74.0 72 74.0 dB
73.5 72 73.5 dB
25°C V
25°C II
25°C V
74.5 74.5 dB
74.0 72 74.0 dB
73.0 73.0 dB
25°C V
25°C II
25°C V
92 92 dBc
90 83 90 dBc
85 85 dBc
25°C V
25°C II
25°C V
Full V
93 93 dBc
92 85 92 dBc
92 92 dBc
100 100 dBFS
Full V
25°C V
90 90 dBc
250 250 MHz
1 See the Explanation of Test Levels section.
2 AVCC = 5 V to 5.25 V for rated ac performance.
3 Analog input signal power swept from −7 dBFS to −100 dBFS.
4 F1 = 15 MHz, F2 = 15.5 MHz.
Rev. D | Page 5 of 24

6 Page









AD6644 pdf, datenblatt
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
ENCODE = 65MSPS
AIN = 15.5MHz @ –29.5dBFS
NO DITHER
5 10 15 20 25
FREQUENCY (MHz)
Figure 16. 1M FFT Without Dither
30
100
ENCODE = 65MSPS
90 AIN = 15.5MHz
NO DITHER
80
70
60
50
40
30
SFDR = 90dB
REFERENCE LINE
20
10
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
ANALOG INPUT POWER LEVEL (dBFS)
Figure 17. SFDR Without Dither
0
AD6644
95
2.2MHz
90 WORST SPUR
85
30.5MHz
ENCODE = 65MSPS
80
2.2MHz
SNR
75
30.5MHz
70
65
–15
–10 –5
0
5 10
ENCODE INPUT POWER (dBm)
15
Figure 18. SNR, Worst Spurious vs. Clamped Encode Power (See Figure 27)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
ENCODE = 65MSPS
AIN = 15.5MHz @ –29.5dBFS
DITHER @ –19dBm
5 10 15 20 25
FREQUENCY (MHz)
Figure 19. 1M FFT with Dither
30
100
90
ENCODE = 65MSPS
AIN = 15.5MHz
DITHER = –19dBm
80
70
60
50
SFDR = 100dB
40 REFERENCE LINE
30
20
SFDR = 90dB
REFERENCE LINE
10
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
ANALOG INPUT POWER LEVEL (dBFS)
Figure 20. SFDR with Dither
0
Rev. D | Page 11 of 24

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