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PDF AS28F128J3A Data sheet ( Hoja de datos )
| Número de pieza | AS28F128J3A | |
| Descripción | 128Mb x8 and x16 Q-FLASH Memory | |
| Fabricantes | Micross | |
| Logotipo |  |
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Austin Semiconductor, Inc.
AS28AFS2182FP812EJP83JEM3AMM
Q-FQl-aFslahsh
Plastic Encapsulated Microcircuit
P1l2a8sMticb,Exn8caanpdsux1la6teQd-FMLiAcSroHciMrceumitory
1E2v8eMn Sbe,cxt8oraedn,dSxin1g6leQB-iFt LpeArSCHellMArecmhiotrecyture
EFvEenATSeUcRtoEreSd, Single Bit per Cell Architecture
F•e atu10r0e%s Pin and Function compatible to Intel’s MLC Family
• NOR Cell Architecture
•• 1020.7%VPtion3a.n6dVFVunCcCtion compatible to Intel’s MLC Family
•• N2O.7RVCteoll3A.6rVchiotrec5tVureVPEN (Programming Voltage)
•• 2.A7Vsytnoc3h.r6oVnoVuCs CPage Mode Reads
•• 2.M7Vantouf3a.c6tVureorr’5sVIDVCPEodNe:(Programming Voltage)
• Asy ncNhruomnoounsyPxa0gxe8M9hode Reads
•• MIannduufsatcrtyurSetra’nsdIaDrdCPodine-:Out
• FulMlyTc2o8mF1p2at8iJb3leMTRTGL Input aMnidcrOonutputs 0x2Ch
•• InCdousmtrmy oSntaFnldaasrhd IPnitne-rOfaucte [CFI]
•• FuSlclyalcaobmlepCatoibmlemTaTndL SInept ut and Outputs
•• CAomutmomonaFtilcasWh RInItTeErfaacned[CEFRIA] SE Algorithms
•• Sc5a.6laubslepeCroBmymteanedffSecetive programming time
•• A1u2to8mbaiticprWotRecItTioEnarnedgEisRteAr SE Algorithms
• 5.6u s p6e4r-bBiyttueneifqfuecetidveevpicreogirdaemntmifinegr time
• 128 bi6t 4p-rbotiet cutsioenr prerogigsrtaemr mable OTP cells
•
•
ESench66ua44rn--ibbctyiiettdOuusndTeiaqPrtuapberploodrgocerkvtaeimcfceetmiaoitadunberlfneeetiaOftiuTerrPe
with
cells
use
of
VPEN=VSS
•• E1nh0a0n,0c0ed0 dEaRtaApSrEoteccytciolensfpeaetruBreLwOiCthKuse of VPEN=VSS
•• SeAcuutroitmy aOtiTcPSbulsopceknfdeaOtuprteions:
•
•
•
•
A1A0Auv0tav o,i0EBBPalma0iRnllBBPEMlboo0aahORnllltccbaieooiEhkklGOclncc-ReOacTEEkkRSGnAeOpeuRRAcdEERemSspeAArMRRpAEdeapeSStAAr eMnicaEESnrSSdytaUgiSScEEStnOSulRUUUgerSSPp[saSSeSRt-EUUni EpPPPoaNg[[SSeEET--nEnerEXDPPNNssg]NB:EE:T-TeDDtDLNNso]]--: O ---ttDDRoot4Co--0--E-PR--ttKoRoo45ACRE--05EDORPAootAoCCREGDD+OARttoo1GDA0++R5M11oAC0255MooCC
Mil-Temperature [-XT] -55oC to +125oC
For in-depth functional product detail and Timing Diagrams,
please reference Numonyx’s full product Datasheet:
For in-depth functional product detail and Timing Diagrams,
plEeMasBe EreDfeDreEnDceFMLAicrSoHn’Ms fEuMll pOrRoYdu(cJt3D-6a5tansmhe)et:
Dated: March 2010
MT28F640J3 Rev. L Dated 04/16/04
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RP\
A11
A10
A9
A8
VSS
A7
A6
A5
A4
A3
A2
A1
PIN ASSIGNMENT
123 456 78
A
A1 A6
B
A2 VSS
C
A3
A7
D
A4
A5
E
DQ8 DQ1
F
BYTE\ DQ0
G
A23
A0
H
CE2 DNU
A8 VPEN A13 VCC A18
A9 CE0 A14 DNU A19
A10 A12 A15 DNU A20
A11 RP\ DNU DNU A16
DQ9 DQ3 DQ4 DNU DQ15
DQ10 DQ11 DQ12 DNU DNU
DQ2 VCCQ DQ5 DQ6 DQ14
VCC VSS DQ13 VSS DQ7
A22
CE1
A21
A17
STS
OE\
WE\
DNU
64-Ball FBGA
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
NC
WE\
OE\
STS
DQ15
DQ7
DQ14
DQ6
VSS
DQ13
DQ5
DQ12
DQ4
VCCQ
VSS
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE\
A23
CE2
General Description
GENERAL DESCRIPTION
AMSIi’csr,oAssS'2A8FS12288FJ132M8JE3nAhaEncnehdanocr eMdilo-Tr eMmipl-vTaermiapnt voafrMiainctroonf’s
QN-Fulmasohnyfaxm’silyQ-oFfladsehvicfeasm, iilsy aofnodnevvoilcaetisl,e,iselaecntroicnavlloylabtliolec,k-
eucooedtarosnreaslienecen8svethcag,hai3itbnitucr8nhloniee8iMceldno,ar6(rgmilg1Fec0lydy6Lra18.o,n3Aab7nbT4unl7S’yo,hdfs72Htacie,1tskc2)ws70,dt-1,e(u.ee7p81xnrrv2r51ate(oi8yuxs6cdgam8)eerbb.)iauciglmtooesTshprinmth(nro8tFo1eagar,Lc2i3gbdne8a8ANleisenK8nvsSui,gBizm6Hmce10eteEd)eo38m,ciR4nsapbho,Aysrny2uroxyoSt1neeg’lE7iisosdrtf,haog7e(b0emrxyv2lmro.1.i8m1cc61le5byk)a6ius.b,tms.7sTmTlee7aochh7ntrimeposg,u2rrdafe1eoanmedd8ccvietzoeiuwv(ecrsxridyiesec8tdhe)
TaasTCticonolohhogdCfmbiimteosswoepprmdmdiaeautetenorhsimvevdbnemiiedioiccFlnssienefLttody,tffAFor.eeeJvEaSLaebtitnHDAucueterriESIree-uneCiHsssntefeiidIanrndIDefm--napss-tfciyyieeloneisnsrerdttf[deseeaCeemmpconFneefttInbbi,]drd[llJetoeoCehEvccnaFfDkikttacIEemwp]llooseCi.ticcrthlhmkkiIaTeiiDifntnshtogs-geprio..wsnesfodroaTTfmderfthhdtwpewieeevtaayysanirncredadaeseleolasssinblfo.sogtatwodhcwhTrkeaaaiivwhvtrtvhiheeeaecmredas-
forward and backward compatibility.
is uniformly sectored with one hundred and twenty eight 128KB
ERASE blocks.
AS28F128J3MRG
Revision 5.0 11/23/04
AS28F128J3A
Rev. 5.8 8/13
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
1 Micross Components reserves the right to change products or specifications without notice.
1
1 page  
DC Voltage specifications
PEM
AS28F128J3A
Q-Flash
Symbol
VIL
VIH
VCCQ
VCC
Parameter
Input Low Voltage
Input High Voltage
2.7 ‐ 3.6V
2.7 ‐ 3.6V
Min Max Units
‐0.5 0.8
V
2.0 VCCQ+0.5
V
Test Conditions
‐
‐
Notes
2,5,6
2,5,6
VOL Output Low Voltage
VCC = VCCMin
‐ 0.4 V VCCQ = VCCQ Min
IOL = 2 mA
VCC = VCCMin
‐ 0.2 V VCCQ = VCCQ Min
IOL = 100 µA
1,2
VOH
VPENLK
VPENH
VLKO
Output High Voltage
VPEN Lockout during Program,
Erase and Lock‐Bit Operations
VPEN during Block Erase, Program,
or Lock‐Bit Operations
VCC Lockout Voltage
0.85 × VCCQ
VCCQ – 0.2
‐
2.7
‐
‐
‐
2.2
3.6
2.0
VCC = VCCMin
VCCQ = VCCQ Min
V IOH = 2.5 mA
VCC = VCCMin
VCCQ = VCCQ Min
IOH = 100 µA
V
V
V
‐
‐
‐
1,2
2,3
3
4
Notes
1. Includes STS.
2. Sampled, not 100% tested.
3. Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min),
and above VPENH (max).
4. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above
VCC (max).
5. Includes all operational modes of the device.
6. Input/Output signals can undershoot to -1.0V referenced to VSS and can overshoot to VCCQ + 1.0V for duration of 2ns or less, the VCCQ valid range is referenced to VSS.
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
ReTseatbSlpee1ci4fi:catRioensset Specifications
PEM
AS28F128J3A
Q-Flash
Ta#b#le 14SS:yymmRbboeolsl et Specifications
PaPraarmaemteetrer
Min Min Max MaUxnit UNnoittes
# Symbol
PP11 tPtLPPLHPH
P1
P2
P2
P3
NPPo32tes:
tPLPH
tPHRH
tPHRH
tttPVHCRCHPH
VCCPH
R(sR(RsaR(saIpPIIppfpPPPfef#e Rep##p#cRRclcPil iPPfPiiPciH#ficfu##ciauicaialc gbisallibstisasshlestielee toiteto)ittLi nioe)LiLoneoedoonidwdRsiww st iettsonTo nosT ToinVeom iVitmVotmCtCeCCtdeCe,Cu,t,rth ihtnihsigsisBlPocaRkrRpPaRpoRpEPr#mrpPPr#roooae##Rgeiggssir rPstiierraass#eaaa,tm a sraammiPsoisssssreon ssoeoorraeegrrtrsrrotler ooslttelapodoeeecpdmeckdrdcedkrt-dk,r au-ebddau‐btordbituuirtiirointiiorrdntcnLgiicn ugonnocornbggocnbilnf k nolfirbo-ggiefcglBcuiokagurkirtecduraekaaertr tdriaaeoiaotsrnsienaoe,sn,e,
aCRpoPpn#lif ciHgaiubgrlhea) ttioon Reset during Block ERraPs#e,is Parossgerratmed, dour rLinogckr‐eBaidt
RVCPco#cnPfHiogigwuherartotVioaRnleidsettodRuPr#ingdeB-laoscskeErtriaosne,(hPirgohg)ram, or Lock-Bit
CVocncf iPgourwaetiro nValid to RP# de‐assertion (high)
M2in5 25 Ma—x ‐Unµist
21500 100 ——
— 100
100 ‐ —
60 —
— 60 100
‐ µnss
ns
100ns
µs
‐ ns
Nµost1es
ns11
1,2
ns1
—
µ1s,2
N1.oTtehNse12soP..e3tespse:cifiTAcathVtrieCoesCnsesPeHtasrpteiemvcaieVlfi,idcctcafoPtHrPioaQolnVwl ,sperioasrdrVrueeacqvtlivuadeliirrtdseoidofRnofsPrro#(apmlaldcpektahr-ogaeedsslsuaeactnrtttedvirosenporesf(eihSodinsTg)sS.h()(pinacRkYa/gBeYs#anmdodspee)eodrsR).P#
60
going high
—
until outputs
µs
are
valid.
—
2. A r1e.set time,TtPhHeQseV,sisperecqifuiicreadtiforonms tahreelavttaelridoffSoTrSa(lilnpRrYo/dBuYc#tmvoedres)ioonr Rs P(#pagcokinaggheigshaunndtil souptepeutdssa)r.e valid.
7.4 AC Test Conditions2. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
AC7FIi.gn4puurte/O1u3t:puAtACRCeIfneTrpeuentcs/etOWuCatvopeunfotrdRmietfieornensce Waveform
Notes
1
1
1,2
‐
Figure 13: AC InVpCCuQt/Output Reference Waveform
Input
VCC0Q.0
VCCQ/2
Test Points
VCCQ/2 Output
Input VCCQ/2
Test Points
VCCQ/2 Output
NoteNs ote:
AC test inputs
AVarCCeCdtQer/ivs2etnVinap(t 5Vu0Cts%CaQ0rofe.of0rdVarCiLCvoQeg)ni.caI"1nt"pVauCntCdQr0is.f0oeVraafnodrLaofgaLoilclgti"ci1m""0e.a"snIn(dp1u00t%.t0imVtinogfo9br0eg%ainL)so,<agni5cd
"0." Input timing begins,
onust.put timing ends, at VCCQ/2
and output timing ends, at
V (50% of VCCQ). Input rise and
fall
times
(10%NFotiotge9u0:%r)eA<C51tn4ess.:t Tinrpautns sairee ndrtivEenqautiVvCaCQlefonrtaTLoegsicti"n1"ganLdo0a.0dVCfoirrcauLiotgic "0." Input timing begins, and output timing ends, at
VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
TrFaingsuiernet E14qu: iTvaralennst iTeensttinEgqLuoivaadlCenirtcuTiet sting Load Circuit
Device
UDndeevricTeest
Under Test
Out
CL
Out
CL
Note: CL Includes Jig Capacitance
NToateb:leC1L 5In:cluTdeessJtigCCoapnafciitgauncreation
Table 15: Test CToesntfCigonufrigautriaotnion
Test Configuration
VCCQ = VCCQMIN
Test Configuration
Test ConfigurVaCtCiQo=n VCCQMIN
VCCQ = VCCQMIN
CL (pF)
30
CL (pF)
30
CL (pF)
30
ARSev2.85FM2.180a28r88c0/hJ313223-A00120
March 2010
208032-02
11
Micross Components reserves the right to change products or speciDficaattioansshweit2he9otut notice.
Datasheet
29
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AS28F128J3A.PDF ] | |
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