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AD7656-1 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7656-1
Beschreibung 16-/14-/12-Bit ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD7656-1 Datasheet, Funktion
Data Sheet
250 kSPS, 6-Channel, Simultaneous
Sampling, Bipolar, 16-/14-/12-Bit ADC
AD7656-1/AD7657-1/AD7658-1
FEATURES
Pin and software compatible with AD7656/AD7657/AD7658
featuring reduced decoupling requirements
6 independent ADCs
True bipolar analog inputs
Pin-/software-selectable ranges: ±10 V, ±5 V
Fast throughput rate: 250 kSPS
iCMOS process technology
Low power
140 mW at 250 kSPS with 5 V supplies
High noise performance with wide bandwidth
88 dB SNR at 10 kHz input frequency
On-chip reference and reference buffers
High speed parallel, serial, and daisy-chain interface modes
High speed serial interface
SPI/QSPI™/MICROWIRE™/DSP compatible
Standby mode: 315 µW maximum
64-lead LQFP
APPLICATIONS
Power line monitoring and measuring systems
Instrumentation and control systems
Multiaxis positioning systems
GENERAL DESCRIPTION
The AD7656-1/AD7657-1/AD7658-11 are reduced decoupling pin-
and software-compatible versions of AD7656/AD7657/AD7658.
The AD7656-1/AD7657-1/AD7658-1 devices contain six 16-/
14-/12-bit, fast, low power successive approximation ADCs in
a package designed on the iCMOS® process (industrial CMOS).
iCMOS is a process combining high voltage silicon with submicron
CMOS and complementary bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no previous generation
of high voltage parts could achieve. Unlike analog ICs using conven-
tional CMOS processes, iCMOS components can accept bipolar
input signals while providing increased performance, which
dramatically reduces power consumption and package size.
The AD7656-1/AD7657-1/AD7658-1 feature throughput rates
of up to 250 kSPS. The parts contain low noise, wide bandwidth
track-and-hold amplifiers that can handle input frequencies
up to 4.5 MHz.
FUNCTIONAL BLOCK DIAGRAM
VDD CONVST A CONVST B CONVST C AVCC DVCC
REF
CLK
OSC
CONTROL
LOGIC
V1 T/H
BUF
16-/14-/
12-BIT SAR
OUTPUT
DRIVERS
CS
SER/PAR SEL
VDRIVE
STBY
DB8/DOUT A
V2 T/H
V3 T/H
BUF
16-/14-/
12-BIT SAR
16-/14-/
12-BIT SAR
OUTPUT
DRIVERS
OUTPUT
DRIVERS
DB6/SCLK
DB9/DOUT B
DB10/DOUT C
V4 T/H
V5 T/H
V6 T/H
BUF
16-/14-/
12-BIT SAR
16-/14-/
12-BIT SAR
OUTPUT
DRIVERS
DATA/
CONTROL
LINES
RD
16-/14-/
12-BIT SAR
AD7656-1/AD7657-1/AD7658-1
WR/REFEN/DIS
VSS AGND DGND
Figure 1.
The conversion process and data acquisition are controlled
using the CONVST signals and an internal oscillator. Three
CONVST pins (CONVST A, CONVST B, and CONVST C)
allow independent, simultaneous sampling of the three ADC
pairs. The AD7656-1/AD7657-1/AD7658-1 have a high speed
parallel and serial interface, allowing the devices to interface with
microprocessors or DSPs. When the serial interface is selected,
each part has a daisy-chain feature that allows multiple ADCs to
connect to a single serial interface. The AD7656-1/AD7657-1/
AD7658-1 can accommodate true bipolar input signals in the
±4 × VREF and ±2 × VREF ranges. Each AD7656-1/AD7657-1/
AD7658-1 also contains an on-chip 2.5 V reference.
PRODUCT HIGHLIGHTS
1. Six 16-/14-/12-bit, 250 kSPS ADCs on board.
2. Six true bipolar, high impedance analog inputs.
3. High speed parallel and serial interfaces.
4. Reduced decoupling requirements and reduced bill of
materials cost compared with the AD7656/AD7657/
AD7658 devices.
1 Protected by U.S. Patent No. 6,731,232.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.






AD7656-1 Datasheet, Funktion
AD7656-1/AD7657-1/AD7658-1
Parameter
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating-State Leakage Current
Floating-State Output Capacitance2
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time1,2
Throughput Rate
POWER REQUIREMENTS
VDD
VSS
AVCC
DVCC
VDRIVE
ITOTAL3
Normal Mode—Static
Min Typ
VDRIVE − 0.2
Twos
complement
−5
−5
4.75
4.75
2.7
Normal Mode—Operational
ISS (Operational)
IDD (Operational)
Partial Power-Down Mode
Full Power-Down Mode (STBY Pin)
Power Dissipation
Normal Mode—Static
Normal Mode—Operational
Partial Power-Down Mode
Full Power-Down Mode
(STBY Pin)
1 See the Terminology section.
2 Sample tested during initial release to ensure compliance.
3 Includes IAVCC, IVDD, IVSS, IVDRIVE, and IDVCC.
Max
0.2
±10
10
3.1
550
250
+16.5
−16.5
5.25
5.25
5.25
18
26
0.25
0.25
7
60
94
140
40
315
Unit
V
V
µA
pF
µs
ns
kSPS
V
V
V
V
V
mA
mA
mA
mA
mA
µA
mW
mW
mW
µW
Data Sheet
Test Conditions/Comments
ISOURCE = 200 µA
ISINK = 200 µA
Parallel interface mode only
For the 4 × VREF range, VDD = 10 V to 16.5 V
For the 4 × VREF range, VSS= −10 V to −16.5 V
Digital inputs = 0 V or VDRIVE
AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V,
VSS = −16.5 V
fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = +5.25 V, VDD =
+16.5 V, VSS = −16.5 V
VSS = −16.5 V, fSAMPLE = 250 kSPS
VDD = 16.5 V, fSAMPLE = 250 kSPS
AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V,
VSS = −16.5 V
SCLK on or off, AVCC = DVCC = VDRIVE = +5.25 V,
VDD = +16.5 V, VSS = −16.5 V
AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V,
VSS = −16.5 V
fSAMPLE = 250 kSPS
Rev. D | Page 6 of 32

6 Page









AD7656-1 pdf, datenblatt
AD7656-1/AD7657-1/AD7658-1
Data Sheet
Pin No.
19
20
63
18
51
61
17
16
15
14
13
12
11
10
Mnemonic
CS
RD
WR/REFEN/DIS
BUSY
REFIN/REFOUT
SER/PAR SEL
DB0/SEL A
DB1/SEL B
DB2/SEL C
DB3/DCIN C
DB4/DCIN B
DB5/DCIN A
DB6/SCLK
DB7/HBEN/DCEN
Description
Chip Select. This active low logic input frames the data transfer. If both CS and RD are logic low and
the parallel interface is selected, the output bus is enabled and the conversion result is output on
the parallel data bus lines. If both CS and WR are logic low and the parallel interface is selected, DB[15:8]
are used to write data to the on-chip control register. When the serial interface is selected, the CS is
used to frame the serial read transfer and clock out the MSB of the serial output data.
Read Data. If both CS and RD are logic low and the parallel interface is selected, the output bus is
enabled. When the serial interface is selected, the RD line should be held low.
Write Data/Reference Enable and Disable. When the H/S SEL pin is high and both CS and WR are
logic low, DB[15:8] are used to write data to the internal control register. When the H/S SEL pin is
low, this pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the
internal reference is disabled and an external reference should be applied to the REFIN/REFOUT pin.
When H/S SEL = 0 and REFEN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin
should be decoupled. See the Internal/External Reference section.
Busy Output. This pin transitions to high when a conversion is started and remains high until the
conversion is complete and the conversion data is latched into the output data registers. A new
conversion cannot be initiated on the AD7656-1/AD7657-1/AD7658-1 when the BUSY signal is high
because any applied CONVST edges are ignored.
Reference Input/Reference Output. The on-chip reference is available via this pin. Alternatively, the
internal reference can be disabled and an external reference can be applied to this input. See the
Internal/External Reference section. When the internal reference is enabled, decouple this pin using
at least a 1 µF decoupling capacitor.
Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is high,
the serial interface is selected. When the serial interface is selected, DB[10:8] function as DOUT[C:A],
DB[0:2] function as DOUT, and DB7 functions as DCEN. When the serial interface is selected, tie DB15 and
DB[13:11] to DGND.
Data Bit 0/Select DOUT A. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output
pin. When SER/PAR SEL = 1, this pin functions as SEL A and is used to configure the serial interface. If
this pin is 1, the serial interface operates with one, two, or three DOUT output pins and enables
DOUT A as a serial output. When the serial interface is selected, always set this pin to 1.
Data Bit 1/Select DOUT B. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output
pin. When SER/PAR SEL = 1, this pin functions as SEL B and is used to configure the serial interface. If
this pin is 1, the serial interface operates with two or three DOUT output pins and enables DOUT B
as a serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial data output pin
and only one DOUT output pin, DOUT A, is used. Unused serial DOUT pins should be left unconnected.
Data Bit 2/Select DOUT C. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output
pin. When SER/PAR SEL = 1, this pin functions as SEL C and is used to configure the serial interface. If
this pin is 1, the serial interface operates with three DOUT output pins and enables DOUT C as a
serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data output pin.
Unused serial DOUT pins should be left unconnected.
Data Bit 3/Daisy-Chain Input C. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When the serial
interface is selected but the device is not used in daisy-chain mode, tie this pin to DGND.
Data Bit 4/Daisy-Chain Input B. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital
output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When the serial
interface is selected but the device is not used in daisy-chain mode, tie this pin to DGND.
Data Bit 5/Daisy-Chain Input A. When SER/PAR SEL is low, this pin acts as a three-state parallel digital
output pin. When SER/PAR SEL = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When the serial
interface is selected but the device is not used in daisy-chain mode, tie this pin to DGND.
Data Bit 6/Serial Clock. When SER/PAR SEL = 0, this pin acts as a three-state parallel digital output pin.
When SER/PAR SEL = 1, this pin functions as SCLK input and is the read serial clock for the serial transfer.
Data Bit 7/High Byte Enable/Daisy-Chain Enable. When the parallel interface is selected and the device is
used in word mode (SER/PAR SEL = 0 and W/B = 0), this pin functions as Data Bit 7. When the parallel
interface is selected and the device is used in byte mode (SER/PAR SEL = 0 and W/B = 1), this pin
functions as HBEN. If the HBEN pin is logic high, the data is output MSB byte first on DB[15:8]. If the
HBEN pin is logic low, the data is output LSB byte first on DB[15:8]. When the serial interface is
selected (SER/PAR SEL = 1), this pin functions as DCEN. If the DCEN pin is logic high, the parts
operate in daisy-chain mode with DB[5:3] functioning as DCIN[A:C]. When the serial interface is
selected but the device is not used in daisy-chain mode, this pin should be tied to DGND.
Rev. D | Page 12 of 32

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