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PDF AD7177-2 Data sheet ( Hoja de datos )
| Número de pieza | AD7177-2 | |
| Descripción | Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs
Settling and True Rail-to-Rail Buffers
AD7177-2
FEATURES
GENERAL DESCRIPTION
32-bit data output
Fast and flexible output rate: 5 SPS to 10 kSPS
Channel scan data rate of 10 kSPS/channel (100 µs settling)
Performance specifications
19.1 noise free bits at 10 kSPS
20.2 noise free bits at 2.5 kSPS
24.6 noise free bits at 5 SPS
INL: ±1 ppm of FSR
85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling
User configurable input channels
2 fully differential channels or 4 single-ended channels
Crosspoint multiplexer
On-chip 2.5 V reference (±2 ppm/°C drift)
True rail-to-rail analog and reference input buffers
The AD7177-2 is a 32-bit low noise, fast settling, multiplexed,
2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital
converter (ADC) for low bandwidth inputs. It has a maximum
channel scan rate of 10 kSPS (100 µs) for fully settled data. The
output data rates range from 5 SPS to 10 kSPS.
The AD7177-2 integrates key analog and digital signal condition-
ing blocks to allow users to configure an individual setup for
each analog input channel in use. Each feature can be user selected
on a per channel basis. Integrated true rail-to-rail buffers on the
analog inputs and external reference inputs provide easy to drive
high impedance inputs. The precision 2.5 V low drift (2 ppm/°C)
band gap internal reference (with output reference buffer) adds
embedded functionality to reduce external component count.
Internal or external clock
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
Power supply: AVDD1 − AVSS = 5 V, AVDD2 = IOVDD = 2.5 V
at a 27.27 SPS output data rate. The user can switch between
to 5 V
different filter options according to the demands of each
Split supply with AVDD1/AVSS at ±2.5 V
channel in the application. The ADC automatically switches
ADC current: 8.4 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
Serial port interface (SPI), QSPI, MICROWIRE, and DSP
compatible
APPLICATIONS
through each selected channel. Further digital processing
functions include offset and gain calibration registers,
configurable on a per channel basis.
The device operates with a 5 V AVDD1 supply, or with ±2.5 V
AVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD supplies.
The specified operating temperature range is −40°C to +105°C.
Process control: PLC/DCS modules
The AD7177-2 is available in a 24-lead TSSOP package.
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA
REF– REF+ REFOUT
IOVDD REGCAPD
CROSSPOINT
MULTIPLEXER
1.8V
LDO
RAIL-TO-RAIL
REFERENCE
INPUT BUFFERS
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
AIN0
AIN1
AIN2
AIN3
AIN4
AVDD RAIL-TO-RAIL
ANALOG INPUT
BUFFERS
Σ-Δ ADC
INT
REF
DIGITAL
FILTER
SERIAL
INTERFACE
AND CONTROL
AVSS
TEMPERATURE
SENSOR
AVSS
GPIO AND
MUX
I/O CONTROL
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AD7177-2
GPIO0 GPIO1
XTAL1 XTAL2/CLKIO
Figure 1.
DGND
CS
SCLK
DIN
DOUT/RDY
SYNC/ERROR
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7177-2
Data Sheet
SPECIFICATIONS
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,
internal master clock (MCLK) = 16 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1.
Parameter
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR)
No Missing Codes1
Resolution
Noise
FIR Filter Rejection
ACCURACY
Integral Nonlinearity (INL)
Offset Error2
Offset Drift
Gain Error2
Gain Drift
REJECTION
Power Supply Rejection
Common-Mode Rejection
At DC
At 50 Hz, 60 Hz1
Normal Mode Rejection1
ANALOG INPUTS
Differential Input Range
Absolute Voltage Limits1
Input Buffers Disabled
Input Buffers Enabled
Analog Input Current
Input Buffers Disabled
Input Current
Input Current Drift
Input Buffers Enabled
Input Current
Input Current Drift
Crosstalk
INTERNAL REFERENCE
Output Voltage
Initial Accuracy3
Temperature Coefficient1
0°C to 105°C
−40°C to +105°C
Reference Load Current, ILOAD
Power Supply Rejection
Load Regulation
Test Conditions/Comments
See Table 19 to Table 23
See Table 19 to Table 23
See Table 23
All input buffers disabled
All input buffers enabled
Internal short
Internal short
All input buffers disabled
All input buffers enabled
AVDD1, AVDD2, VIN = 1 V
VIN = 0.1 V
20 Hz output data rate (post filter),
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (postfilter)
External clock, 20 SPS ODR (postfilter)
VREF = (REF+) − (REF−)
External clock
Internal clock (±2.5% clock)
AVDD1 − 0.2 V to AVSS + 0.2 V
AVDD1 to AVSS
1 kHz input
100 nF external capacitor to AVSS
REFOUT, with respect to AVSS
REFOUT, TA = 25°C
AVDD1, AVDD2 (line regulation)
∆VOUT/∆ILOAD
Min
5
32
95
120
71
85
AVSS − 0.05
AVSS
−0.12
−10
Typ
±1
±3.5
±40
±80
±45
±2.5
±0.4
95
90
90
±VREF
±48
±0.75
±4
±30
±75
±1
−120
2.5
±2
±3
90
32
Max
10,000
Unit
SPS
Bits
±3.5
±7.8
±100
±40
±0.75
ppm of FSR
ppm of FSR
µV
nV/°C
ppm of FSR
ppm of FSR
ppm/°C
dB
dB
dB
dB
dB
V
AVDD1 + 0.05 V
AVDD1
V
+0.12
±5
±10
+10
µA/V
nA/V/°C
nA/V/°C
nA
pA/°C
nA/°C
dB
V
% of V
ppm/°C
ppm/°C
mA
dB
ppm/mA
Rev. B | Page 4 of 60
5 Page 
AD7177-2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
AIN4 1
24 AIN3
REF– 2
23 AIN2
REF+ 3
22 AIN1
REFOUT 4
21 AIN0
REGCAPA 5
AVSS 6
AVDD1 7
AD7177-2
TOP VIEW
(Not to Scale)
20 GPIO1
19 GPIO0
18 REGCAPD
AVDD2 8
17 DGND
XTAL1 9
16 IOVDD
XTAL2/CLKIO 10
15 SYNC/ERROR
DOUT/RDY 11
14 CS
DIN 12
13 SCLK
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions1
Pin No. Mnemonic Type2 Description
1 AIN4
AI Analog Input 4. This pin is electable through the crosspoint multiplexer.
2 REF−
AI Reference Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V.
3 REF+
AI Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+
can span from AVSS + 1 V to AVDD1. The device functions with a reference magnitude from 1 V to AVDD1.
4
REFOUT
AO Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS.
5
REGCAPA
AO Analog Low Dropout (LDO) Regulator Output. Decouple this pin to AVSS using a 1 µF and a 0.1 µF
capacitor.
6 AVSS
P Negative Analog Supply. This supply ranges from −2.75 V to 0 V and is nominally set to 0 V.
7 AVDD1 P Analog Supply Voltage 1. This voltage is 5 V ± 10% with respect to AVSS. AVDD1 − AVSS can be a single
5 V supply or a ±2.5 V split supply.
8 AVDD2 P Analog Supply Voltage 2. This voltage ranges from 2 V to 5 V with respect to AVSS.
9 XTAL1
AI Input 1 for Crystal.
10 XTAL2/CLKIO AI/DI Input 2 for Crystal/Clock Input or Output. The functionality of this pin is based on the CLOCKSEL bits in
the ADCMODE register. There are four options available for selecting the MCLK source:
Internal oscillator: no output.
Internal oscillator: output to XTAL2/CLKIO. Operates at IOVDD logic level.
External clock: input to XTAL2/CLKIO. Input must be at IOVDD logic level.
External crystal: connected between XTAL1 and XTAL2/CLKIO.
11
DOUT/RDY DO
Serial Data Output/Data Ready Output. DOUT/RDY is a dual purpose pin. It functions as a serial data
output pin to access the output shift register of the ADC. The output shift register can contain data
from any of the on-chip data or control registers. The data-word/control word information is placed on
the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the
DOUT/RDY output is three-stated. When CS is low, DOUT/RDY operates as a data ready pin, going low
to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes
high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a
processor, indicating that valid data is available.
12 DIN
DI Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register address (RA) bits of the communications register
identifying the appropriate register. Data is clocked in on the rising edge of SCLK.
13 SCLK
DI Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a
Schmitt triggered input, making the interface suitable for opto-isolated applications.
14 CS
DI Chip Select Input. This pin is an active low logic input used to select the ADC. CS can be used to select
the ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the
ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. When CS
is high, the DOUT/RDY output is three-stated.
Rev. B | Page 10 of 60
11 Page | ||
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