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PDF AD7176-2 Data sheet ( Hoja de datos )
| Número de pieza | AD7176-2 | |
| Descripción | Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
24-Bit, 250 kSPS Sigma-Delta ADC
with 20 µs Settling
AD7176-2
FEATURES
Fast and flexible output rate—5 SPS to 250 kSPS
Fast settling time—20 µs
Channel scan data rate of 50 kSPS/channel
Performance specifications
17 noise free bits at 250 kSPS
20 noise free bits at 2.5 kSPS
22 noise free bits at 5 SPS
INL ±2.5 ppm of FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
User-configurable input channels
2 fully differential or 4 pseudo differential
Crosspoint multiplexer
On-chip 2.5 V reference (drift 2 ppm/°C)
Internal oscillator, external crystal, or external clock
Power supply
Single supply: 5 V AVDD1, 2 V to 5 V AVDD2 and IOVDD
Optional split supply: AVDD1 and AVSS ± 2.5 V
Current: 7.8 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
CRC error checking
SPI, QSPI, MICROWIRE, and DSP compatible
APPLICATIONS
Process control: PLC/DCS modules
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
GENERAL DESCRIPTION
The AD7176-2 is a fast settling, highly accurate, high resolution,
multiplexed Σ-Δ analog-to-digital converter (ADC) for low band-
width input signals. Its inputs can be configured as two fully
differential or four pseudo differential inputs via the integrated
crosspoint multiplexer. An integrated precision, 2.5 V, low drift
(2 ppm/°C), band gap internal reference (with an output
reference buffer) adds functionality and reduces the external
component count.
The maximum channel scan data rate is 50 kSPS/channel
(settling time of 20 µs), resulting in fully settled data with
17 noise free bits. User-selectable output data rates range from
5 SPS to 250 kSPS. The resolution increases at lower speeds.
The AD7176-2 offers three key digital filters. The fast settling
sinc5 + sinc1 filter maximizes the channel scan rate. The sinc3
filter maximizes the resolution for single-channel, low speed
applications. For 50 Hz and 60 Hz environments, the AD7176-2
specific filter minimizes the settling times or maximizes the
rejection of the line frequency. These enhanced filters enable
simultaneous 50 Hz and 60 Hz rejection with a 27 SPS output
data rate (with a settling time of 36 ms).
System offset and gain errors can be corrected on a per channel
basis. This per channel configurability extends to the output data
rate used for each channel when using a sinc5 + sinc1 filter. All
switching of the crosspoint multiplexer is controlled by the ADC
and can be configured to automatically control an external
multiplexer via the GPIO pins.
The specified operating temperature range is −40°C to +105°C.
The AD7176-2 is housed in a 24-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT
IOVDD REGCAPD
1.8V
LDO
BUFFERED
PRECISION
REFERENCE
1.8V
LDO
AIN0
AIN1
AIN2
AIN3
AIN4
INT
REF
Σ-Δ ADC
DIGITAL
FILTER
SERIAL
INTERFACE
AND CONTROL
GPIO AND
MUX
I/O CONTROL
CROSSPOINT
MULTIPLEXER
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
AVSS
GPIO0 GPIO1
XTAL1 CLKIO/XTAL2
Figure 1.
AD7176-2
DGND
CS
SCLK
DIN
DOUT/RDY
SYNC/ERROR
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7176-2
Data Sheet
SPECIFICATIONS
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,
internal master clock = 16 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR)
No Missing Codes1
Resolution
Noise
Noise Free Resolution
ACCURACY
Integral Nonlinearity (INL)
Offset Error2
Offset Drift
Offset Drift vs. Time3
Gain Error2
Gain Drift vs. Temperature1
Gain Drift vs. Time3
REJECTION
Power Supply Rejection
Common-Mode Rejection
At DC
At 50 Hz and 60 Hz1
Normal Mode Rejection1
ANALOG INPUTS
Differential Input Voltage Range
Absolute AIN Voltage Limits1
Analog Input Current
Input Current
Input Current Drift
Crosstalk
INTERNAL REFERENCE
Output Voltage
Initial Accuracy1
Temperature Coefficient
Reference Load Current, ILOAD
Power Supply Rejection (Line
Regulation)
Load Regulation
Voltage Noise
Voltage Noise Density
Turn-On Settling Time
Test Conditions/Comments
Excluding sinc3 filter ≥125 kSPS
See Table 6
See Table 6
Sinc5 + sinc1 filter (default)
250 kSPS, REF+ = 5 V
2.5 kSPS, REF+ = 5 V
5 SPS, REF+ = 5 V
2.5 V reference
5 V reference
Internal short
Internal short
25°C
Min
5
24
AVDD1, AVDD2 VIN = 1 V
VIN = 0.1 V
20 SPS ODR (post filter)
(50 Hz ± 1 Hz and 60 Hz ± 1 Hz)
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (post filter)
External clock, 20 SPS ODR (post filter)
95
130
71
85
AVSS − 0.050
External clock
Internal clock (±2.5 % clock)
1 kHz input
100 nF external capacitor on REFOUT
to AVSS
REFOUT with respect to AVSS
TA = 25°C4
− 0.16%
0°C to +105°C
−40°C to +105°C
IL
AVDD1 and AVDD2
−10
∆VOUT/∆IL
eN, 0.1 Hz to 10 Hz
eN, 1 kHz
100 nF capacitor
Rev. D | Page 4 of 68
Typ
17.3
20.1
22.4
±2.5
±7
±40
±110
±450
±10
±0.5
±3
90
90
90
±VREF
±48
±0.75
±4
−120
2.5
±2
±3
93
32
4.5
215
60
Max
250,000
Unit
SPS
Bits
Bits
Bits
Bits
±7 ppm of FSR
ppm of FSR
µV
nV/°C
nV/1000
hours
±50 ppm/FSR
±1 ppm/FSR/°C
ppm/FSR/
1000 hours
dB
dB
dB
dB
dB
AVDD1 + 0.05
V
V
µA/V
nA/V/°C
nA/V/°C
dB
+ 0.16%
±5
±10
+10
V
V
ppm/°C
ppm/°C
mA
dB
ppm/mA
µV rms
nV/√Hz
µs
5 Page 
AD7176-2
Pin No.
15
Mnemonic
SYNC/ERROR
16 IOVDD
17 DGND
18 REGCAPD
19 GPIO0
20 GPIO1
21 AIN0
22 AIN1
23 AIN2
24 AIN3
Data Sheet
Description
Can be switched between a logic input and a logic output in the GPIOCON register. When synchronization
input is enabled, this pin allows for synchronization of the digital filters and analog modulators when
using multiple AD7176-2 devices. When synchronization input is disabled, this pin can be used in one of
three modes:
Active low error input mode: this mode sets the ADC_ERROR bit in the STATUS register.
Active low, open-drain error output mode: the STATUS register error bits are mapped to the ERROR pin.
The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error
on any device can be observed.
General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON register.
The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the
GPIO pins. The pin has an active pull-up in this case.
Digital I/O Supply Voltage. IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of AVDD2. For
example, IOVDD can be operated at 3 V when AVDD2 equals 5 V, or vice versa. If AVSS is set to −2.5 V, the
voltage on IOVDD must not exceed 3.6 V.
Digital Ground.
Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a
1 µF capacitor.
General-Purpose Input/Output. The pin is referenced between AVDD1 and AVSS levels.
General-Purpose Input/Output. The pin is referenced between AVDD1 and AVSS levels.
Analog Input 0. Selectable through the crosspoint multiplexer.
Analog Input 1. Selectable through the crosspoint multiplexer.
Analog Input 2. Selectable through the crosspoint multiplexer.
Analog Input 3. Selectable through the crosspoint multiplexer.
Rev. D | Page 10 of 68
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7176-2.PDF ] | |
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