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AD9554-1 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9554-1
Beschreibung Multiservice Line Card Adaptive Clock Translator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9554-1 Datasheet, Funktion
Data Sheet
Quad PLL, Quad Input, Multiservice Line
Card Adaptive Clock Translator
AD9554-1
FEATURES
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually no
disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and
ITU-T G.8261
Auto/manual holdover and reference switchover
Adaptive clocking allows dynamic adjustment of feedback
dividers for use in OTN mapping/demapping applications
Quad digital phase-locked loop (DPLL) architecture with four
reference inputs (single-ended or differential)
4 × 4 crosspoint allows any reference input to drive any PLL
Input reference frequencies from 2 kHz to 1000 MHz
Reference validation and frequency monitoring: 2 ppm
Programmable input reference switchover priority
20-bit programmable input reference divider
4 differential clock outputs with each differential pair
configurable as HCSL, LVDS-compatible, or LVPECL-
compatible
Output frequency range: 430 kHz to 941 MHz
Programmable 18-bit integer and 24-bit fractional feedback
divider in digital PLL
Programmable loop bandwidths from 0.1 Hz to 4 kHz
56-lead (8 mm × 8 mm) LFCSP package
APPLICATIONS
Network synchronization, including synchronous Ethernet
and synchronous digital hierarchy (SDH) to optical
transport network (OTN) mapping/demapping
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient
control
Cable infrastructure
Data communications
Professional video
GENERAL DESCRIPTION
The AD9554-1 is a low loop bandwidth clock translator that
provides jitter cleanup and synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9554-1 generates an output clock synchronized to up to four
external input references. The digital PLLs (DPLLs) allow
reduction of input time jitter or phase noise associated with the
external references. The digitally controlled loop and holdover
circuitry of the AD9554-1 continuously generates a low jitter
output clock even when all reference inputs have failed.
The AD9554-1 operates over an industrial temperature range of
−40°C to +85°C. The AD9554 is a version of this device with
two outputs per PLL. If a single or dual DPLL version of this
device is needed, refer to the AD9557 or AD9559, respectively.
STABLE
SOURCE
FUNCTIONAL BLOCK DIAGRAM
STATUS AND
CONTROL PINS
REFERENCE
INPUT
MONITOR
AND MUX
CLOCK
MULTIPLIER
SERIAL INTERFACE
(SPI OR I2C)
DIGITAL
PLL0
DIGITAL
PLL1
DIGITAL
PLL2
DIGITAL
PLL3
ANALOG
PLL0
ANALOG
PLL1
ANALOG
PLL2
ANALOG
PLL3
÷3 TO ÷11
P0 DIVIDER
÷3 TO ÷11
P1 DIVIDER
÷3 TO ÷11
P2 DIVIDER
÷3 TO ÷11
P3 DIVIDER
AD9554-1
Figure 1.
Q0_B DIVIDER
Q1_B DIVIDER
Q2_B DIVIDER
Q3_B DIVIDER
Rev. B
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AD9554-1 Datasheet, Funktion
AD9554-1
Data Sheet
POWER DISSIPATION
Typical (typ) values apply for VDD = 1.8 V and maximum (max) values for VDD = 1.89 V.
Table 3.
Parameter
POWER DISSIPATION
Typical Configuration
All Blocks Running
Full Power-Down
Incremental Power Dissipation
Complete DPLL/APLL On/Off
Input Reference On/Off
Differential (Normal Mode)
Differential (DC-Coupled LVDS)
Single-Ended
Output Distribution Driver On/Off
28 mA Mode (at 644.53 MHz)
21 mA Mode (at 644.53 MHz)
14 mA mode (at 644.53 MHz)
Min Typ Max Unit
0.92 1.1 W
1.02 1.2 W
164 mW
190 mW
22.5 mW
24.6 mW
14.3 mW
70 mW
48 mW
23.6 mW
Test Conditions/Comments
System clock: 49.152 MHz crystal; four DPLLs active;
two 19.44 MHz input references in differential mode;
four ac-coupled output drivers in 21 mA mode at
644.53125 MHz
System clock: 49.152 MHz crystal; four DPLLs active,
four 19.44 MHz input references in differential mode;
eight ac-coupled output drivers in 28 mA mode at
750 MHz
Measured using the Typical Configuration parameter
(see Table 3) and then setting the full power down bit
Typical configuration; table values show the change in
power due to the indicated operation
Power delta computed relative to the typical
configuration; the blocks powered down include one
reference input, one DPLL, one APLL, one P divider, two
channel dividers, two output drivers in 28 mA mode
fREF = 19.44 MHz
fREF = 19.44 MHz
fREF = 19.44 MHz
SYSTEM CLOCK INPUTS (XOA, XOB)
Table 4.
Parameter
Min Typ Max Unit Test Conditions/Comments
SYSTEM CLOCK MULTIPLIER
PLL Output Frequency Range
2250
2415 MHz
Voltage controlled oscillator (VCO) range can place
limitations on nonstandard system clock input frequencies
Phase Frequency Detector (PFD) Rate
10
300 MHz
Frequency Multiplication Range
8
241 Assumes valid system clock and PFD rates
SYSTEM CLOCK REFERENCE INPUT PATH
System clock input must be ac-coupled
Input Frequency Range
System Clock Input Doubler Disabled 10
268 MHz
System Clock Input Doubler Enabled 16
150 MHz
Minimum Input Slew Rate
250
V/µs Minimum limit imposed for jitter performance
Self-Biased Common-Mode Voltage
0.72 V Internally generated
Input High Voltage
0.9 V For ac-coupled single-ended operation
Input Low Voltage
0.5 V
For ac-coupled single-ended operation
Differential Input Voltage Sensitivity
250
mV p-p
Minimum voltage across pins required to ensure switching
between logic states; the instantaneous voltage on either
pin must not exceed 1.14 V; single-ended input can be
accommodated by ac grounding complementary input;
800 mV p-p recommended for optimal jitter performance
Rev. B | Page 6 of 99

6 Page









AD9554-1 pdf, datenblatt
AD9554-1
Data Sheet
DIGITAL PLL LOCK DETECTION
Table 12.
Parameter
PHASE LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
FREQUENCY LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
Min Typ Max Unit
10
1
224 − 1 ps
ps
10
1
224 − 1 ps
ps
Test Conditions/Comments
Reference-to-feedback phase difference
Reference-to-feedback period difference
HOLDOVER SPECIFICATIONS
Table 13.
Parameter
HOLDOVER SPECIFICATIONS
Initial Frequency Accuracy
Min Typ Max Unit
Test Conditions/Comments
<0.01
ppm Excludes frequency drift of SYSCLK source; excludes
frequency drift of input reference prior to entering
holdover; compliant with GR-1244 Stratum 3
SERIAL PORT SPECIFICATIONS—SERIAL PORT INTERFACE (SPI) MODE
Table 14.
Parameter
CS
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO
As an Input
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
As an Output
Output Logic 1 Voltage
Output Logic 0 Voltage
Min
VDD_SP − 0.4
VDD_SP − 0.4
Typ Max
0.4
1
1
3
0.4
1
1
2
Unit Test Conditions/Comments
Valid for VDD_SP = 1.5 V, VDD_SP = 1.8 V, and VDD_SP = 2.5 V
V
V
µA
µA
pF
No internal pull-up or pull-down resistor
V
V
µA
µA
pF
VDD_SP − 0.4
1
1
2
VDD_SP − 0.2
V
0.4 V
µA
µA
pF
V
0.1 V
1 mA load current
1 mA load current
Rev. B | Page 12 of 99

12 Page





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