|
|
PDF AD9163 Data sheet ( Hoja de datos )
| Número de pieza | AD9163 | |
| Descripción | RF DAC and Digital Upconverter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9163 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
16-Bit, 12 GSPS,
RF DAC and Digital Upconverter
AD9163
FEATURES
DAC update rate up to 12 GSPS (minimum)
Direct RF synthesis at 6 GSPS (minimum)
DC to 3 GHz in nonreturn-to-zero (NRZ)mode
DC to 6 GHz in 2× NRZ mode
1.5 GHz to 7.5 GHz in Mix-Mode
Selectable interpolation
6×, 8×, 12×, 16×, 24×
Excellent dynamic performance
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
MC-GSM, W-CDMA, LTE, LTE-A, point to point
GENERAL DESCRIPTION
bandwidth of up to 1 GHz and the complex NCO and digital
upconverter enable dual band and triple band direct RF
synthesis of wireless infrastructure signals, eliminating costly
analog upconverters.
Wide analog bandwidth capability combines with high dynamic
range to support DOCSIS 3.1 cable infrastructure compliance
from the minimum of one carrier up to 1 GHz of signal bandwidth,
making it ideal for cable multiple dwelling unit (MDU) applications.
A 2× interpolator filter (FIR85) enables the AD9163 to be config-
ured for lower data rates and converter clocking to reduce the
overall system power and ease the filtering requirements. In
Mix-Mode™ operation, the AD9163 can reconstruct RF carriers
in the second and third Nyquist zones up to 7.5 GHz while still
maintaining exceptional dynamic range. The output current can
be programmed from 8 mA to 38.76 mA. The AD9163 data
interface consists of up to eight JESD204B serializer/deserializer
(SERDES) lanes that are programmable in terms of lane speed
and number of lanes to enable application flexibility.
The AD91631 is a high performance, 16-bit digital-to-analog
converter (DAC) that supports data rates to 6 GSPS. The DAC
core is based on a quad-switch architecture coupled with a 2×
interpolator filter that enables an effective DAC update rate of
up to 12 GSPS in some modes. The high dynamic range and
bandwidth makes this DAC ideally suited for the most
demanding high speed radio frequency (RF) DAC applications.
Superior RF performance and deep interpolation rates enable
use of the AD9163 in many wireless infrastructure applications,
including MC-GSM, W-CDMA, LTE, and LTE-A. The wide
A serial peripheral interface (SPI) configures the AD9163 and
monitors the status of all the registers. The AD9163 is offered in
a 169-ball, 11 mm × 11 mm, 0.8 mm pitch CSP_BGA package.
PRODUCT HIGHLIGHTS
1. High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface, flexible in
terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet multiband wireless
communications standards with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET IRQ
ISET VREF
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
SPI
JESD
HB
2×
HB
3×
AD9163
HB
2×
NCO
VREF
NRZ RZ MIX
INV
SINC
DAC
CORE
OUTPUT±
HB
TO JESD
CLOCK
2×,
TO DATAPATH
DISTRIBUTION
4×,
8×
TX_ENABLE
Figure 1.
CLK±
1 Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9163
Data Sheet
DAC INPUT CLOCK OVERCLOCKING SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Maximum guaranteed speed using the temperatures and voltages conditions as shown in Table 2, where VDDx is VDD12_CLK, DVDD,
VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any DAC clock speed over 5.1 GSPS requires a maximum junction temperature of
105°C to avoid damage to the device. See Table 10 for details on maximum junction temperature permitted for certain clock speeds.
Table 2.
Parameter1
MAXIMUM DAC UPDATE RATE
VDDx = 1.2 V ± 5%
VDDx = 1.2 V ± 2%
VDDx = 1.3 V ± 2%
Test Conditions/Comments
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
Min Typ Max Unit
6.0 GSPS
5.6 GSPS
5.4 GSPS
6.1 GSPS
5.8 GSPS
5.6 GSPS
6.4 GSPS
6.2 GSPS
6.0 GSPS
1 TJMAX is the maximum junction temperature.
POWER SUPPLY DC SPECIFICATIONS
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. FIR85 is the finite impulse response with 85 dB digital attenuation.
Table 3.
Parameter
8 LANES, 6× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
8 LANES, 8× INTERPOLATION (80%), 5 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
Test Conditions/Comments
NCO on, FIR85 on
Min
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
NCO on, FIR85 off (unless otherwise noted)
NCO on, FIR85 off
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
Rev. 0 | Page 4 of 123
−119
Typ Max
93.8
3.7
228.7
−120.7
598.4
2.5
443.4
72.3
81.8
9.4
94
80
341
−112
495
2.5
477
89
81
9.3
100
150
435
878
2.7
681
130
112
11
Unit
mA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
mA
mA
mA
mA
mA
mA
mA
mA
5 Page 
AD9163
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7 8 9 10 11 12 13
A VSS
VNEG_N1P2 VDD25_DAC VNEG_N1P2 VDD25_DAC OUTPUT–
OUTPUT+ VDD25_DAC VNEG_N1P2 VDD25_DAC
VSS
ISET
VREF
A
B CLK+
VSS
VSS
VDD25_DAC VNEG_N1P2 VDD25_DAC VDD25_DAC VNEG_N1P2 VDD25_DAC
VDD12A
VDD12A
VDD25_DAC VNEG_N1P2 B
C CLK–
VSS
VSS
VSS
VDD25_DAC VNEG_N1P2 VNEG_N1P2 VDD25_DAC VBG_NEG
VSS
VSS
VSS
VSS
C
D VSS
VDD12_CLK VDD12_CLK VDD12_CLK VDD12_CLK
VSS
VSS
VDD12_CLK VDD12_CLK VDD12_CLK VDD12_CLK VDD12_CLK VDD12_CLK D
E VDD12_CLK
VSS
VSS
VSS
DVDD
DVDD
VSS
DVDD
DVDD
VSS
VSS
VSS
VSS
E
F SYSREF+
SYSREF–
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CS
VSS
F
G VSS
VSS
TX_ENABLE
IRQ
DVDD
DVDD
DVDD
DVDD
DVDD
SDIO
SDO
VSS
VSS
G
H SERDIN7+
SERDIN7–
VDD_1P2
RESET
IOVDD
DVDD_1P2
VSS
DVDD_1P2
IOVDD
SCLK
VDD_1P2
SERDIN0–
SERDIN0+ H
J VSS
VSS
VDD_1P2
DNC
DNC
VSS
VSS
VSS
SYNCOUT– SYNCOUT+
VDD_1P2
VSS
VSS
J
K SERDIN6+
SERDIN6–
VTT_1P2
SYNC_
VDD_3P3
DNC
VSS
PLL_CLK_
VDD12
PLL_LDO_
VDD12
DNC
SYNC_
VDD_3P3
VTT_1P2
SERDIN1–
SERDIN1+ K
L VSS
VSS
VDD_1P2
VDD_1P2
VDD_1P2
VSS
DNC
VSS
VDD_1P2
VDD_1P2
VDD_1P2
VSS
VSS
L
M VSS
VSS
SERDIN5+
VSS
SERDIN4+
VSS
PLL_LDO_
BYPASS
VSS
SERDIN3+
VSS
SERDIN2+
VSS
VSS
M
N BIAS_VDD_1P2
VSS
SERDIN5–
VSS
SERDIN4–
VSS
VSS
VSS
SERDIN3–
VSS
SERDIN2–
VSS
BIAS_
VDD_1P2
N
123
–1.2V ANALOG SUPPLY
2.5V ANALOG SUPPLY
1.2V DAC SUPPLY
GROUND
DNC = DO NOT CONNECT.
4 56
1.2V DAC CLK SUPPLY
SERDES INPUT
SERDES 3.3V VCO SUPPLY
SERDES 1.2V SUPPLY
7
89
DAC RF SIGNALS
SYSREF±/SYNCOUT±
CMOS I/O
IOVDD
10 11
REFERENCE
12
Figure 4. 169-Ball CSP_BGA Pin Configuration
13
Table 12. 169-Ball CSP_BGA Pin Function Descriptions
Pin No.
A1, A11, B2, B3, C2, C3, C4, C10, C11, C12, C13, D1, D6, D7, E2, E3,
E4, E7, E10, E11, E12, E13, F3, F4, F5, F6, F7, F8, F9, F10, F11, F13,
G1, G2, G12, G13, H7, J1, J2, J6, J7, J8, J12, J13, K6, L1, L2, L6, L8,
L12, L13, M1, M2, M4, M6, M8, M10, M12, M13, N2, N4, N6, N7, N8,
N10, N12
A2, A4, A9, B5, B8, B13, C6, C7
A3, A5, A8, A10, B4, B6, B7, B9, B12, C5, C8
A6
A7
A12
Mnemonic
VSS
VNEG_N1P2
VDD25_DAC
OUTPUT−
OUTPUT+
ISET
A13 VREF
B1, C1
B10, B11
C9
CLK+, CLK−
VDD12A
VBG_NEG
D2, D3, D4, D5, D8, D9, D10, D11, D12, D13, E1
E5, E6, E8, E9, G5, G6, G7, G8, G9
VDD12_CLK
DVDD
Description
Supply Return. Connect these pins to ground.
−1.2 V Analog Supply Voltage.
2.5 V Analog Supply Voltage.
DAC Negative Current Output.
DAC Positive Current Output.
Reference Current. Connect this pin to
VNEG_N1P2 with a 9.6 kΩ resistor.
1.2 V Reference Input/Output. Connect this pin
to VSS with a 1 µF capacitor.
Positive and Negative DAC Clock Inputs.
1.2 V Analog Supply Voltage.
−1.2 V Reference. Connect this pin to
VNEG_N1P2 with a 0.1 µF capacitor.
1.2 V Clock Supply Voltage.
1.2 V Digital Supply Voltage.
Rev. 0 | Page 10 of 123
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9163.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9161 | RF Digital-to-Analog Converters | Analog Devices |
| AD9162 | RF Digital-to-Analog Converters | Analog Devices |
| AD9163 | RF DAC and Digital Upconverter | Analog Devices |
| AD9164 | RF DAC and Direct Digital Synthesizer | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |