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AD9136 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9136
Beschreibung Digital-to-Analog Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9136 Datasheet, Funktion
Data Sheet
Dual, 11-/16-Bit, 2.8 GSPS, TxDAC+®
Digital-to-Analog Converters
AD9135/AD9136
FEATURES
Support input data rate >2 GSPS
Proprietary low spurious and distortion design
SFDR = 82 dBc at dc IF, −9 dBFS
Flexible 8-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Selectable 1×, 2×, 4×, or 8× interpolation filter
Low power architecture
Transmit enable function allows extra power saving and
instant control of the output status
High performance, low noise phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter
Low power: 1.42 W at 1.6 GSPS full operating conditions
88-lead LFCSP with exposed pad
APPLICATIONS
Wireless communications
3G/4G W-CDMA base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point
Local multipoint distribution service (LMDS) and
multichannel multipoint distribution service (MMDS)
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
The AD9135/AD9136 are dual, 11-/16-bit, high dynamic range
digital-to-analog converters (DACs) that provide a maximum
sample rate of 2800 MSPS, permitting a multicarrier generation
over a very wide bandwidth. The DAC outputs are optimized to
interface seamlessly with the ADRF6720, as well as other analog
quadrature modulators (AQMs) from Analog Devices, Inc. An
optional 3-wire or 4-wire serial port interface (SPI) provides for
programming/readback of many internal parameters. The full-
scale output current can be programmed over a typical range of
13.9 mA to 27.0 mA. The AD9135/AD9136 are available in an
88-lead LFCSP.
TYPICAL APPLICATION CIRCUIT
QUAD MOD
ADRF6720
LPF
SYSREF±
RF OUTPUT
0°/90° PHASE
SHIFTER
LO_IN MOD_SPI
DAC
DAC
AD9135/
AD9136
JESD204B
SYNCOUT0±
SYNCOUT1±
Figure 1.
CLK±
DAC
SPI
PRODUCT HIGHLIGHTS
1. Greater than 2 GHz, ultrawide complex signal bandwidth
enables emerging wideband and multiband wireless
applications.
2. Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
3. JESD204B Subclass 1 support simplifies multichip
synchronization in software and hardware design.
4. Fewer pins for data interface width with a serializer/
deserializer (SERDES) JESD204B eight-lane interface.
5. Programmable transmit enable function allows easy design
balance between power consumption and wake-up time.
6. Small package size with 12 mm × 12 mm footprint.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9136 Datasheet, Funktion
AD9135/AD9136
Data Sheet
DIGITAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input Voltage (VIN) Logic
High
Low
CMOS OUTPUT LOGIC LEVEL
Output Voltage (VOUT) Logic
High
Low
MAXIMUM DAC UPDATE RATE1
ADJUSTED DAC UPDATE RATE
INTERFACE4
Number of JESD204B Lanes
JESD204B Serial Interface Speed
Minimum
Maximum
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK5 Frequency (PLL Mode)
SYSTEM REFERENCE INPUT
(SYSREF+, SYSREF−)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
SYSREF± Frequency6
SYSREF SIGNAL TO DAC CLOCK7
Setup Time
Hold Time
Keep Out Window
SPI
Maximum Clock Rate
Minimum SCLK Pulse Width
High
Low
SDIO to SCLK
Setup Time
Hold Time
Symbol Test Conditions/Comments
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
1× interpolation2 (see Table 4)
2× interpolation2
4× interpolation3
8× interpolation3
1× interpolation
2× interpolation
4× interpolation
8× interpolation
Per lane
Per lane, SVDD12 = 1.3 V ± 2%
Self biased input, ac-coupled
6.0 GHz ≤ fVCO ≤ 12.0 GHz
tSSD
tHSD
KOW
SCLK
tPWH
tPWL
tDS
tDH
SYSREF differential swing = 0.4 V, slew
rate = 1.3 V/ns, common modes tested:
ac-coupled, 0 V, 0.6 V, 1.25 V, 2.0 V
IOVDD = 1.8 V
Min
0.7 × IOVDD
0.75 × IOVDD
2120
2120
2800
2800
2120
1060
700
350
10.64
400
2800
35
400
0
131
119
10
5
2
Typ
8
1000
600
1000
20
Max
0.3 × IOVDD
0.25 × IOVDD
1.44
2000
1000
2000
2000
fDATA/(K × S)
8
12
Unit
V
V
V
V
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
Lanes
Gbps
Gbps
mV
mV
MHz
MHz
mV
mV
Hz
ps
ps
ps
MHz
ns
ns
ns
ns
Rev. A | Page 6 of 117

6 Page









AD9136 pdf, datenblatt
AD9135/AD9136
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PVDD12 1
CLK+ 2
CLK– 3
PVDD12 4
SYSREF+ 5
SYSREF– 6
PVDD12 7
PVDD12 8
PVDD12 9
PVDD12 10
TXEN0 11
TXEN1 12
DVDD12 13
DVDD12 14
SERDIN0+ 15
SERDIN0– 16
SVDD12 17
SERDIN1+ 18
SERDIN1– 19
SVDD12 20
VTT 21
SVDD12 22
AD9135/AD9136
TOP VIEW
(Not to Scale)
66 IOVDD
65 CS
64 SCLK
63 SDIO
62 SDO
61 RESET
60 IRQ
59 PROTECT_OUT0
58 PROTECT_OUT1
57 PVDD12
56 PVDD12
55 GND
54 GND
53 DVDD12
52 SERDIN7+
51 SERDIN7–
50 SVDD12
49 SERDIN6+
48 SERDIN6–
47 SVDD12
46 VTT
45 SVDD12
Data Sheet
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE.
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin No. Mnemonic
1 PVDD12
2 CLK+
3 CLK−
4 PVDD12
5 SYSREF+
6 SYSREF−
7 PVDD12
8 PVDD12
9 PVDD12
10 PVDD12
11 TXEN0
12 TXEN1
13 DVDD12
14 DVDD12
15 SERDIN0+
16 SERDIN0−
17 SVDD12
18 SERDIN1+
Description
1.2 V Supply. PVDD12 provides a clean supply.
PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input.
When the PLL is not used, this pin is the positive device clock input. This pin is self biased and must be
ac-coupled.
PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input.
When the PLL is not used, this pin is the negative device clock input. This pin is self biased and must be
ac-coupled.
1.2 V Supply. PVDD12 provides a clean supply.
Positive Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled
or dc-coupled.
Negative Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled
or dc-coupled.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
Transmit Enable for DAC0. CMOS levels are determined with respect to IOVDD.
Transmit Enable for DAC1. CMOS levels are determined with respect to IOVDD.
1.2 V Digital Supply.
1.2 V Digital Supply.
Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 0, Negative. CML compliant. SERDIN0− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Rev. A | Page 12 of 117

12 Page





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