Datenblatt-pdf.com


AD9161 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9161
Beschreibung RF Digital-to-Analog Converters
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9161 Datasheet, Funktion
Data Sheet
11-Bit/16-Bit, 12 GSPS,
RF Digital-to-Analog Converters
AD9161/AD9162
FEATURES
DAC update rate up to 12 GSPS (minimum)
Direct RF synthesis at 6 GSPS (minimum)
DC to 2.5 GHz in baseband 1× bypass mode
DC to 6 GHz in 2× nonreturn-to-zero (NRZ) mode
1.5 GHz to 7.5 GHz in Mix-Mode
Bypassable interpolation (1× or bypass mode)
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
Excellent dynamic performance
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
W-CDMA, LTE, LTE-A, point to point
Instrumentation, automatic test equipment (ATE)
Radars and jammers
GENERAL DESCRIPTION
In baseband mode, wide bandwidth capability combines with
high dynamic range to support DOCSIS 3.1 cable infrastructure
compliance from the minimum of two carriers to full maximum
spectrum of 1.794 GHz. A 2× interpolator filter (FIR85) enables
the AD9161/AD9162 to be configured for lower data rates and
converter clocking to reduce the overall system power and ease
the filtering requirements. In Mix-Mode™ operation, the AD9161/
AD9162 can reconstruct RF carriers in the second and third
Nyquist zones up to 7.5 GHz while still maintaining exceptional
dynamic range. The output current can be programmed from
8 mA to 38.76 mA. The AD9161/AD9162 data interface consists
of up to eight JESD204B serializer/deserializer (SERDES) lanes
that are programmable in terms of lane speed and number of
lanes to enable application flexibility.
A serial peripheral interface (SPI) can configure the AD9161/
AD9162 and monitor the status of all registers. The AD9161/
AD9162 are offered in an 165-ball, 8.0 mm × 8.0 mm, 0.5 mm
pitch, CSP_BGA package and in an 169-ball, 11 mm × 11 mm,
0.8 mm pitch, CSP_BGA package, including a leaded ball
option for the AD9162.
The AD9161/AD91621 are high performance, 11-bit/16-bit
PRODUCT HIGHLIGHTS
digital-to-analog converters (DACs) that supports data rates to
6 GSPS. The DAC core is based on a quad-switch architecture
coupled with a 2× interpolator filter that enables an effective
DAC update rate of up to 12 GSPS in some modes. The high
dynamic range and bandwidth makes these DACs ideally suited
for the most demanding high speed radio frequency (RF) DAC
applications.
1. High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in
terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1
compliance with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET IRQ
ISET VREF
SDIO
SDO
CS
SCLK
SERDIN0±
SERDIN7±
SYNCOUT±
SYSREF±
SPI
JESD
HB
HB
AD9161/AD9162
HB
NCO
VREF
NRZ RZ MIX
INV
SINC
DAC
CORE
OUTPUT±
HB
TO JESD
CLOCK
2×,
TO DATAPATH
DISTRIBUTION
4×,
TX_ENABLE
Figure 1.
CLK±
1 Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD9161 Datasheet, Funktion
AD9161/AD9162
Data Sheet
Parameter
8 LANES, 3× INTERPOLATION (80%), 4.5 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD1 = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
POWER DISSIPATION
3 GSPS
NRZ Mode, 2×, FIR85 Enabled, NCO On
2× NRZ Mode, 6×, FIR85 Enabled, NCO On
2× NRZ Mode, 4×, FIR85 Enabled, NCO On
2× NRZ Mode, 1×, FIR85 Enabled, NCO On
NRZ Mode, 24×, FIR85 Disabled, NCO On
5 GSPS
NCO Mode, FIR85 Disabled, NCO On
NRZ Mode, 4×, FIR85 Disabled, NCO On
2× NRZ Mode, 4x, FIR85 Enabled, NCO Off
2× NRZ Mode, 4×, FIR85 Enabled, NCO On
NRZ Mode, 8×, FIR85 Disabled, NCO On
NRZ Mode, 16×, FIR85 Disabled, NCO On
2× NRZ Mode, 6×, FIR85 Enabled, NCO On
NRZ Mode, 3×, FIR85 Disabled, NCO On (4.5 GSPS)
1 IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance.
Test Conditions/Comments
NCO on, FIR85 on
Includes VDD12_DCD/DLL
IOVDD = 2.5 V
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 3× filter, eight-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
1× bypass mode (AD9162 only), eight-lane
JESD204B
Using 80%, 2× filter, one-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 3× filter, eight-lane JESD204B
Using 80%, 3× filter, six-lane JESD204B
Min
Typ Max Unit
94
85
314.3
−112.1
175
948.5
2.5
432.3
62.3
84.7
9.2
mA
µA
mA
mA
mA
mA
mA
mA
mA
mA
2.1 W
2.1 W
2.1 W
1.94 W
1.3 W
1.3 1.83 W
2.3 W
2.35 W
2.58 W
2.18 W
2.09 W
2.65 W
2.62 W
Rev. A | Page 6 of 139

6 Page









AD9161 pdf, datenblatt
AD9161/AD9162
ABSOLUTE MAXIMUM RATINGS
Table 11.
Parameter
ISET, VREF to VBG_NEG
SERDINx±, VTT_1P2,
SYNCOUT±
OUTPUT± to VNEG_N1P2
SYSREF±
CLK± to Ground
RESET, IRQ, CS, SCLK, SDIO,
SDO to Ground
Junction Temperature1
fDAC = 6 GSPS
fDAC ≤ 5.1 GSPS
Ambient Operating
Temperature Range (TA)
Storage Temperature Range
Rating
−0.3 V to VDD25_DAC + 0.3 V
−0.3 V to SYNC_VDD_3P3 + 0.3 V
−0.3 V to VDD25_DAC + 0.3 V
GND − 0.5 V to +2.5 V
−0.3 V to VDD12_CLK + 0.3 V
−0.3 V to IOVDD + 0.3 V
105°C
110°C
−40°C to +85°C
−65°C to +150°C
1 Some operating modes of the device may cause the device to approach or
exceed the maximum junction temperature during operation at supported
ambient temperatures. Removal of heat from the device may require
additional measures such as active airflow, heat sinks, or other measures.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
REFLOW PROFILE
The AD9163 reflow profile is in accordance with the JEDEC
JESD204B criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
THERMAL MANAGEMENT
The AD9163 is a high power device that can dissipate nearly
3 W depending on the user application and configuration.
Because of the power dissipation, the AD9163 uses an exposed
die package to give the customer the most effective method of
controlling the die temperature. The exposed die allows cooling
of the die directly.
Data Sheet
Figure 3 shows the profile view of the device mounted to a user
printed circuit board (PCB) and a heat sink (typically the
aluminum case) to keep the junction (exposed die) below the
maximum junction temperature in Table 11.
CUSTOMER CASE (HEAT SINK)
CUSTOMER THERMAL FILLER
SILICON (DIE)
PACKAGE SUBSTRATE
IC PROFILE
CUSTOMER PCB
Figure 3. Typical Thermal Management Solution
THERMAL RESISTANCE
Typical θJA and θJC values are specified for a 4-layer JEDEC 2S2P
high effective thermal conductivity test board for balled
surface-mount packages. θJA is obtained in still air conditions
(JESD51-2). Airflow increases heat dissipation, effectively reducing
θJA. θJC is obtained with the test case temperature monitored at
the bottom of the package.
ΨJT is thermal characteristic parameters obtained with θJA in still
air test conditions but are not applicable to the CSP_BGA package.
Estimate the junction temperature (TJ) using the following
equations:
TJ = TT + (ΨJT × PDISS)
where:
TT is the temperature measured at the top of the package.
PDISS is the total device power dissipation.
Table 12. Thermal Resistance
Package Type
165-Ball CSP_BGA
169-Ball CSP_BGA
θJA
15.4
14.6
θJC Unit
0.04 °C/W
0.02 °C/W
ESD CAUTION
Rev. A | Page 12 of 139

12 Page





SeitenGesamt 30 Seiten
PDF Download[ AD9161 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD9161RF Digital-to-Analog ConvertersAnalog Devices
Analog Devices
AD9162RF Digital-to-Analog ConvertersAnalog Devices
Analog Devices
AD9163RF DAC and Digital UpconverterAnalog Devices
Analog Devices
AD9164RF DAC and Direct Digital SynthesizerAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche